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Temperature Sensitive Microprocessor Design to Reduce Heat Generation and Improve Performance
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 164 - Number 3 |
| Year of Publication: 2017 |
| Authors: Tamanna Afroze |
10.5120/ijca2017913596
|
Tamanna Afroze . Temperature Sensitive Microprocessor Design to Reduce Heat Generation and Improve Performance. International Journal of Computer Applications. 164, 3 ( Apr 2017), 1-8. DOI=10.5120/ijca2017913596
Abstract
Microprocessors are designed with very tiny microchips and heat induced due to operation makes the chip deteriorate their performance in many extents. Heat causes a portion of chip-area to get heated which degrades operation of many applications in chip-level. This work wants to make a watcher to watch the applications running in pipeline, and then by utilizing slack time in hardware level this work wants to improve performance of the processor. In this paper, this work proposes two new heat-control mechanisms to improve performance, one is at operation-level and the other is at architectural-level. At operation-level, this work proposes a prediction mechanism to predict the useful operations inside the microprocessor that performs as a sink for heat dissipation. At architectural-level, this work proposes a drain system for heat dissipation. The proposed prediction and drain mechanisms will reduce heat generation and thereby increase performance. This work has simulated the proposed system using Matlab and observed that the system works perfectly well. Java program has been devised to take care of fault tolerance and fault detection.
References
- M. Kondo and H. Nakamura, “A Small, Fast and Low-Power Register File by Bit-Partitioning,” Proceedings of the 11th Int’l Symposium on High-Performance Computer Architectur e,2005,pp. 1-10.
- J. Hu, K. John, and S. Wang, “Thermal-Aware Subarrayed Data Cache Microarchitectures,” International Journ al of Intelligent Control and Systems, Vol.13, No. 4, December 2008, pp. 251-263.
- Y. Zhang, D. Parikh, K. Sankaranaraya nan, K. Skadron, and M. Stan, “HotLeakage: A Temperature-Aware Model of Subthreshold and Gate Leakage for Architects,” University of Virginia Department of Computer Science Tech. Report CS-2003-05.
- I. Park, M. D. Powell, and T. N. Vijayku mar, “Reducing Register Ports for Higher Speed and Lower Energy”, In Proceedings of MICRO, 2002.
- M.S. Hrishikesh, N. P. Jouppi, K. I. Farkas, D. Burger, S. W. Keckler, and P. Shivakumar, “The Optimal Logic Depth Per Pipeline Stage is 6 to 8 FO4 Inverter Delays”, In the proceedings of the 29th International Symposium on Computer Architecture.
- J. Donald and M. Martonosi, “Tempera ture Aware Design Issues for SMT and CMP Architectures”, Work shop on Complexity-Effective Design, 2004.
- J. Donald and M. Martonosi, “Techn iques for Multicore Thermal Management: Classification and New E xploration”, ACM SIGARCH Computer Architecture News, 2006.
- Sheng-Chih Lin, N. Srivastava and K. Banerjee, “A Thermally –Aware Methodology for Design –Specific Optimization of Supply and Threshold Voltages in Nanometer Scale ICs”, International Conference of Computer Design, 2005.
- G. H. Loh, Y. Xie, and B. Black, “Proce ssor Design in 3D Die-Stacking Technologies,” IEEE Computer Society, 2007. Pp. 31-48.
- H. Yu, Yu Hu, C. Liu, and Lei He, “Mi nimal Skew Clock Embedding Considering Time Variant Temperature G radient,” In the Proceedings of ISPLD, 2007, Austin, Texas, USA.
- Z. Qi, B. H. Meyer, W. Huang, R. J. Ri bando, K. Skadron, M. R. Stan, “Temperature-to-Power Mapping,” In the Proceedings of ICCD, 2010.
- S. Borkar, “Thousand Core Chips-A T echnology Perspective,” In the Proceedings of DAC, 2007, San Diego, C alifornia, USA.
- J. K. John, J.S. Hu , and S. G. Ziavras, “Optimizing the Thermal Behavior of Subarrayed Data Caches, ” International Conference of Computer Design, 2005.pp. 625-630.
- S. Borkar, “Design Challenges of Technology Scaling,” IEEE Micro, 1999. Pp. 23-29.
- K. Skadron,M. R. Stan, W. Huang, S. Velusamy, K. Sankaranarayanan, and D. Tarjan, “Temperature-Aware M icroarchitecture,” International Symposium on Computer Architecture, 2003.
- O. S. Unsal, J. W. Tschanz, K. Bowman, V. De, X. Vera, A. Gonzales, O. Ergin, “Impact of Parameter Variations on Circuits and Microarchitecture,” In the Proceedings of IEEE Computer Society, 2006, pp. 30-39.
- M. Monchiero, R. Canal, and A. Gonzalez , “Design Space Exploration for Multicore Architectures: A Power/Performance/T hermal View,” In the Proceedings of ICS, 2006, Queensland, Australia.
- Moris Mano, Digital Design, Third Edition.
- K. Sankaranarayanan, S. Velusamy, M. Stan, and K. Skadron,“A case for thermal-aware floorplanning at themicroarchitect ural level.”Journal of Instruction LevelParallelism 8 , 2005, pp. 1-16.
- Web Tools, Online Physics Material Tutorial.
- Matlab, Mathwork’s Simulation Tool.
- B. Zhai, S. Pant, L. Nazhandali, S. Hanson, J. Olson, A. Reeves, and M. Minuth, “Eenergy-Efficient Subthreshold Processor D esign ,” In IEEE
- C. Hamacher, Z. Vranesic, and S. Zaky, “Compputer Organization”, Mc-Graw Hill, Fifth Edition.
- D. A. Patterson, and J.L. Hennessy, Com puter Organization and Design: The Hardware/Software Interface, Elseiver, Third Edition.
- D. A. Patterson, and J.L. Hennessy , Computer Architecture: A Quantitive Approach, Elseiver, Fourth Ed ition.
- I. Hossain, and B. K. Gunturk, “High Dynamic Range Imaging for Non-Static Scenes”, SPIE Electronic Imaging Conference, 2011.
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