The week's pick
Reseach Article
Review Paper on Efficient VLSI Architecture for Carry Select Adder
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 161 - Number 4 |
| Year of Publication: 2017 |
| Authors: Anamika Mandal, Puran Gour, Braj Bihari Soni |
10.5120/ijca2017913137
|
Anamika Mandal, Puran Gour, Braj Bihari Soni . Review Paper on Efficient VLSI Architecture for Carry Select Adder. International Journal of Computer Applications. 161, 4 ( Mar 2017), 4-7. DOI=10.5120/ijca2017913137
Abstract
A adder is one of the key hardware blocks in most digital and high performance systems such as FIR filters, digital signal processors and microprocessors etc. With advances in technology, many researchers have tried and are trying to design many types of adder such as ripple carry adder, carry skip adder, carry a look head adder and carry select adder. Among this adder carry select adder is the high speed, low power consumption and hence less area or even combination of them in adder. However area and speed are two conflicting constraints.
References
- B. Ramkumar and Harish M Kittur, “Low-Power and Area-Efficient Carry Select Adder”, IEEE Transsactions on Very Large Scale Integration (VLSI) Systems, VOL. 20, No. 2 Feb 2012.
- Sajesh Kumar U.a, Mohamed Salih K. K.b Sajith K., “Design and Implementation of Carry Select Adder without Using Multiplexers”, 2012 1st International Conference on Emerging Technology Trends in Electronics, Communication and Networking 978-1-4673-1627-9/12/$31.00 ©2012 IEEE.
- Samiappa Sakthikumaran1, S. Salivahanan, V. S. Kanchana Bhaaskaran2, V. Kavinilavu, B. Brindha and C. Vinoth, “A Very Fast and Low Power Carry Select Adder Circuit”, 978-1-4244 -8679-3 /11/$26.00 ©2011 IEEE.
- Padma Devi, Ashima Girdher, Balwinder Singh, “Improved Carry Select Adder with Reduced Area and Low Power Consumption”, International Journal of Computer Applications (0975 – 8887) Volume 3 – No.4, June 2010.
- Z. Abid, H. El-Razouk and D.A. El-Dib, “Low power multipliers based on new hybrid full adders”, Microelectronics Journal, Volume 39, Issue 12, Pages 1509-1515, 2008.
- Hasan Krad and Aws Yousif Al-Taie, “Performance Analysis of a 32-Bit Multiplier with a Carry-Look-Ahead Adder and a 32-bit Multiplier with a Ripple Adder using VHDL”, Journal of Computer Science 4 (4): 305-308, 2008.
- Wang, Y. Pai, C.Song, X., “The design of hybrid carry look ahead/ carry-select adders”, Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on Volume 49, pp.16-24, 2002.
- YotmgjoonKim and Lee-Sup Kim, “A Low Power Carry Select Adder with Reduced Area”, 0-7803-6685-9/01/$10.0002001 TEEE.
- W. Jeong and K. Roy, “Robust high-performance low power adder”, Proc. of the Asia and South Pacific Design Automation Conference, pp. 503-506, 2003.
- Y. Kim and L-S Kim, “64-bit carry-select adder with reduced area”, Electronics Letters, vol. 37, pp. 614-615, May 2001.
- O. Kwon, E. Swartzlander, and K. Nowka, “A fast hybrid carry-look ahead/carry-select adder design”, Proc. of the 11th Great Lakes symposium on VLSI, pp.149-152, March 2001.
- Adilakshmi Silveru, M. Bharathi, “Design of Kogge-Stone and Brent Kung Adders using Degenerate Pass Transistor Logic”, International Journal of Emerging Science and Engineering Vol.- I , Issue- 4 , Febrnary 2013 .
Index Terms
Keywords