The week's pick
Reseach Article
Testing Technique of BIST: A Survey
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 161 - Number 3 |
| Year of Publication: 2017 |
| Authors: Sakshi Shrivastava, Paresh Rawat, Sunil Malviya |
10.5120/ijca2017913133
|
Sakshi Shrivastava, Paresh Rawat, Sunil Malviya . Testing Technique of BIST: A Survey. International Journal of Computer Applications. 161, 3 ( Mar 2017), 22-25. DOI=10.5120/ijca2017913133
Abstract
As the compactness of system-on-chip (SoC) increase, it becomes striking to integrate dedicated test logic on a chip. Starting with a broad idea of test problems, this survey paper focus on “Chip” Built in Self-Test (BIST) study and its promotion for board and system-level applications. This paper gives brief informative review of Built-in Self-test (BIST) and its testing techniques. Recently BIST Research is being highly used in VLSI and SoC testing for the detection fault coverage.
References
- P. Gadde, “A BIST architecture for testing LUTs in a Virtex-4 FPGA,” 2013.
- R. T. John, K. D. Sreekanth, and S. Sivanantham, “Adaptive Low Power RTPG for BIST based test applications,” 2013 Int. Conf. Inf. Commun. Embed. Syst. ICICES 2013, pp. 933–936, 2013.
- I. Voyiatzis, C. Efstathiou, C. Sgouropoulou, and D. Magos, “Input vector monitoring concurrent BIST with Low hardware overhead.”
- I. Introductiok, “Efficient Parallel Transparent BIST Method for Multiple Embedded Memory Buffers,” 2000.
- B. C. and M. Lubaszewski, “ON-LINE AND OFF-LINE TESTING: FROM DIGITAL TO ANALOG, FROM CIRCUITS TO BOARDS,” IEEE, p. 34.
- P. Fiser and H. Kubatova, “Survey of the Algorithms in the Column-Matching BIST Method,” p. 7695, 2004.
- J. Jahangiri and R. Press, “Test patterns for ICs that are both secure and have very high coverage,” AUTOTESTCON (Proceedings), no. September, pp. 92–96, 2008.
- L. S. A. Low-power, “Short Papers,” vol. 26, no. 2, pp. 396–401, 2007.
- G. Sudhagar, S. Senthil Kumar, G. Ramesh, and G. Sathish Kumar, “Implementation of a novel architecture for VLSI testing,” 2013 Int. Conf. Emerg. Trends VLSI, Embed. Syst. Nano Electron. Telecommun. Syst. ICEVENT 2013, pp. 13–16, 2013.
- S. Remersaro, X. Lin, S. M. Reddy, M. G. Corporation, and W. Lafayette, “Low Shift and Capture Power Scan Tests,” 2007.
- R. Rinitha and R. Ponni, “Testing in VLSI : A Survey.”
- K. Keerthika and A. H. Jeeva Oli, “Online and Offline Testing Of C-Bist Using Sram,” IOSR J. VLSI Signal Process. Ver. II, vol. 5, no. 1, pp. 50–53, 2015.
Index Terms
Keywords