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Reseach Article

A Review on Pipe Line Analog to Digital Converter using 0.18µm CMOS Technology

by Priya Kakaria, Rovin Tiwari
International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 158 - Number 1
Year of Publication: 2017
Authors: Priya Kakaria, Rovin Tiwari
10.5120/ijca2017912725

Priya Kakaria, Rovin Tiwari . A Review on Pipe Line Analog to Digital Converter using 0.18µm CMOS Technology. International Journal of Computer Applications. 158, 1 ( Jan 2017), 23-25. DOI=10.5120/ijca2017912725

@article{ 10.5120/ijca2017912725,
author = { Priya Kakaria, Rovin Tiwari },
title = { A Review on Pipe Line Analog to Digital Converter using 0.18µm CMOS Technology },
journal = { International Journal of Computer Applications },
issue_date = { Jan 2017 },
volume = { 158 },
number = { 1 },
month = { Jan },
year = { 2017 },
issn = { 0975-8887 },
pages = { 23-25 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume158/number1/26873-2017912725/ },
doi = { 10.5120/ijca2017912725 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-07T00:03:40.583450+05:30
%A Priya Kakaria
%A Rovin Tiwari
%T A Review on Pipe Line Analog to Digital Converter using 0.18µm CMOS Technology
%J International Journal of Computer Applications
%@ 0975-8887
%V 158
%N 1
%P 23-25
%D 2017
%I Foundation of Computer Science (FCS), NY, USA
Abstract

This work describes a 12-bit pipeline ADC (Analog-to-Digital Converter) for CMOS (Complementary Metal Oxide Semiconductor) that is implemented in a TSMC 0.18μm CMOS process. The proposed ADC utilizes the Threshold Inverter Quantization (TIQ) technique that uses two cascaded CMOS inverters as a comparator. the TIQ flash ADC achieves high speed, small size, low power consumption, and low voltage operation compared to other ADCs  The sample and hold circuit have high Sampling rate. This Design is implemented and Fabricated in TSMC 0.18μm CMOS verified on the LT SPICE in 0.18µm Technology.

References
  1. A 12-bit 20MS/s 56.3mW Pipelined ADC with Interpolation-Based Nonlinea Calibration Jie Yuan, Member, IEEE, Sheung Wai Fung, Kai Yin Chan, and Ruoyu Xu, Student Member, IEEE 2011
  2. [2 ] Low-Power Pipeline ADC for Wireless LANs J. Arias, V. Boccuzzi, L. Quintanilla,L. Enríquez, D. Bisbal, M. Banu, and J. Barbolla IEEE 2004
  3. [3 ] A 6 BIT 1.2 GSps low power flash ADC IN 0.13um digital CMOS Martin clara andreas santner thamos hartig IEEE 2005
  4. [4 ] A Pipeline Analogue to Digital Converter in 0.35 μm CMOS S.W. Ross†, StudenT Member, IEEE, and S. Sinha Member, IEEE 2007
  5. A 7 bit 16MS/s low power cmos pipeline ADC Zhuang zhaodong ,li zhiqug IEEE 2011
  6. Behazad   Razavi‘Design of Analog CMOS circuit Design’, Tata Mc Graw Hil:
  7. T. B. Cho and P. R. Gray, ‘A 10-bit, 20-MS/s, 35-mW pipeline A/D        converter,’ in Proc. IEEE Custom Integrated Circuits Conf., May 1994,         pp23.2.1-23.2.4 .
  8. phillip E. Allen, Douglas R. Holberg, ‘CMOS Analog circuit Design,’second Edition Oxford university Press. second Edition Oxford university Press.
  9. Razavi B., Wooley B. A., ‘Design Techniques for High- Resolution       comparators’, IEEE Journal of Solid State Circuit, Vol.27, No.12, pp1916-1928, Dec. 1993
  10. R.jacob Baker, Harry W.Li, David E.Boyce, ‘CMOS Circuit Design layout   and simulation,’ IEEE Press.
  11. Patrick Quinn, Maxim Pribytko ‘Capacitor Matching Insensitive 12-bit       3.3MS/s Algorithmic ADC in 0.25pm CMOS’
  12. Analog devices data converters Handbook. Analog Devices Inc.
  13. 13] R.V.D Plassche, ‘CMOS Integrated Analog to Digital and digital to Analog  converters’, 2nd edition: Kluwer Academic publisher, 2003
  14. K.Uyttenhove and M.S.J ‘A 1.12-V 6-bit 1.3-GHz Flash ADC in 0.25µm       CMOS’ IEEE J.of solid-state circuit, pp 111511122, July 2003
  15. A.Abo and P.Gray, ‘A 1[.5-v10-bit 14.3MS/s CMOS Pipeline analog to       digital Converter’, IEEE J.Solid State Circuit, vol.34,pp.599- 605,May.1999
  16. A.Arble and R.Kurz ‘Fast ADC’, IEEE Transaction on Nuclear Science,       vol. NS-22, pp.446-451, Feb.1975.
  17. R.Roovers, M.Steyaert, ‘A 175 Ms/s, 6-b 160-mW 3.3-V CMOS A/D Converter’ IEEE journal of solid-state circuit, vol.31, No.7, pp. 9312-   944, July 1996
  18. S. H. Lewis, et al., ‘10-b 20-Msample/s analog-to-digital converter,’ IEEE J.   Solid-State Circuits, vol. 27, pp.351-3512, March 1992.
  19. J.Ming and S.H Lewis,‘An 12-bit 120-Ms/s pipeline analog to digital converter with Background Calibration,’ IEEE. Of solid-state circuit, pp.14129-97  Oct.2001.
  20. J.Li and U-K Moon ‘Background calibration Technique for multistage pipeline ADCs with digital redundancy,’ IEEE. J.of solid-state circuit,
  21. Tingting Chen 1 heying Li2 Bo Li 3 Yuemei Li4 Chunlei Wang4 Jianjian Wang4 , ‘Improved power scaling issue for Pipeline ADC’, International
Index Terms

Computer Science
Information Sciences

Keywords

Pipe line ADC CMOS transistor