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High Speed Design of FPGA based Golay Encoder and Decoder
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 154 - Number 10 |
| Year of Publication: 2016 |
| Authors: Amit Shrivastava, Mohd. Abdullah |
10.5120/ijca2016912242
|
Amit Shrivastava, Mohd. Abdullah . High Speed Design of FPGA based Golay Encoder and Decoder. International Journal of Computer Applications. 154, 10 ( Nov 2016), 36-42. DOI=10.5120/ijca2016912242
Abstract
In wireless communication systems the most important issue to be considered is the ability of the receiver to detect the errors and correct them from the received information, so as to provide correct information data to the processor. A number of different methods are available to implement the hardware and software with such preference. But, when the length of the communication link becomes very long, i.e., the distance between the wireless transmitter and receiver is very large, the effect of noise on the transmitted signal may cause a change in multiple bits of the transmitted information. This can cause drastic loss in many cases. In this brief a Field Programmable Gate Array (FPGA) based design and simulation of Golay Code (G23) and Extended Golay Code (G24) Encoding scheme are presented. This work is based on the optimization of the time delay of the operational circuit to encode a data packet using the Golay Encoder.
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