The week's pick
Random Articles
Reseach Article
Performance Analysis of Advanced Encryption Standard on FPGA
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 153 - Number 6 |
| Year of Publication: 2016 |
| Authors: Lokesh Namdeo, Himanshu Nautiyal |
10.5120/ijca2016912085
|
Lokesh Namdeo, Himanshu Nautiyal . Performance Analysis of Advanced Encryption Standard on FPGA. International Journal of Computer Applications. 153, 6 ( Nov 2016), 47-51. DOI=10.5120/ijca2016912085
Abstract
The Advanced Encryption Standard is the data security standard referred to as Federal Information Processing Standard 197 (FIPS 197) acquired worldwide by several private and public sectors for protective needs of data storage and secure data application from mobile consumer products to high end user. Most of the AES implementation for reconfigurable devices however based on the configurable logic such as flip-flops and lookup tables. In this paper, all the three modules i.e. AES – 128, AES – 192 and AES – 256 are implemented on Spartan 3 XC3S1000L speed grade -4 FPGA. All the three modules are implemented with four techniques namely, sequential 3 Stage, sequential 2 stage, pipelined and combinational and then a performance of the three techniques is evaluated. At last a combined AES supporting all the three AES types is also implemented using combinational technique. It is observed from the implementations that sequential 2 stage technique is most area efficient technique, whereas pipelined technique is most time efficient technique.
References
- Hammad I, El-Sankary K, El-Masry E, “High-speed AES encryptor with efficient merging techniques,” IEEE Embedded Systems Letters, 2010, pp.67-71.
- I Zhang Y L, Wang X G, “Pipelined implementation of AES encryption based on FPGA,” 2010 IEEE International Conference on Information Theory and Information Security, Piscataway: IEEE, 2010, pp. 170-173.
- Fan C-P, Hwang J-K, “Implementations of high throughput sequential and fully pipelined AES processors on FPGA.” ISPACS 2007: Proceeding of 2007 International Symposium on International Signal Processing and Symposium and Communication Systems, Piscataway: IEEE, 2007, pp. 353-356.
- Sklavos N, Koufopavlou O, “Architectures and VLSI implementations of the AES-proposal Rijndael,” IEEE Transactions on Computers, 2002, 51(12), pp. 1454-1459.
- Borkar A M, Kshirsagar R V, Vyawahare M V, “FPGA implementation of AES algorithm,” The 3rd International Conference on Electronics Computer Technology, Piscataway: IEEE, 2011, 3, pp. 401-405.
- Joan Daemen,Vincent Rijmen.AES Proposal:Rijdael. The Rijndael Block Cipher.
- Vincent Rijmen, “Efficient implementation of the of the rijndael SBox,” 2000.
- Fischer V, Drutarovsky M, Chodowiec P, “InvMixColunm decomposition and multilevel resource sharing in AES implementations,” IEEE Transactions on Very Large Scale Integration Systems, 2005, 13(8), pp. 989-992.
- Chien M Ta, Chee Hong Yong, Wooi Gan Yeoh, “A 2.7mW, 0.064mm2linear-in-dB VGA with 60dB tuningrange, 100MHz bandwidth, and two DC offset cancellation loops,” IEEE International Workshop on Radio Frequency Integration Technology, Austria: Graz, 2005, pp. 74-77.
- J.Balamurugan, Dr.E.Logashanmugam “High Speed Low Cost Implementation of Advanced Encryption Standard on FPGA” ICCET 2014.
Index Terms
Keywords