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Implementation of Decimal - Floating Point ALU Component on Reconfigurable Logic
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 153 - Number 6 |
| Year of Publication: 2016 |
| Authors: Harshit Shrivastava, Himanshu Nautiyal |
10.5120/ijca2016912084
|
Harshit Shrivastava, Himanshu Nautiyal . Implementation of Decimal - Floating Point ALU Component on Reconfigurable Logic. International Journal of Computer Applications. 153, 6 ( Nov 2016), 41-46. DOI=10.5120/ijca2016912084
Abstract
This paper presents the FPGA implementation of a Decimal Floating Point (DFP) arithmetic unit. The design performs addition, subtraction and multiplication on 64-bit operands that use the IEEE 754-2008 DPD encoding of DFP numbers. The design uses an equal bypass adder, this adder reduces the power consumption and it also reduces the delay by reducing the gate count. The design also uses barrel shifter instead of sequential shifter to reduce delay. Also 64 bit parallel BCD multiplier is used to perform fixed point multiplication. The proposed DFP arithmetic unit supports operations on the decimal64 format and it is easily extendable for the decimal128 format.
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