CFP last date
20 January 2025
Call for Paper
February Edition
IJCA solicits high quality original research papers for the upcoming February edition of the journal. The last date of research paper submission is 20 January 2025

Submit your paper
Know more
The week's pick
Responsive image
SFLA-Based Line Balancing and Task Optimization in Master-Slave Controlled Hanger Transportation Systems for Garment Production

Duc Hoang Nguyen
Random Articles
Reseach Article

Design of Input Vector Monitoring Concurrent BIST based Architecture for 4-Bit Multiplier

by Vinay Kumar Pathak, Vinod Kumar Pathak
journal cover thumbnail

International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 153 - Number 5
Year of Publication: 2016
Authors: Vinay Kumar Pathak, Vinod Kumar Pathak
10.5120/ijca2016912055

Vinay Kumar Pathak, Vinod Kumar Pathak . Design of Input Vector Monitoring Concurrent BIST based Architecture for 4-Bit Multiplier. International Journal of Computer Applications. 153, 5 ( Nov 2016), 19-24. DOI=10.5120/ijca2016912055

@article{ 10.5120/ijca2016912055,
author = { Vinay Kumar Pathak, Vinod Kumar Pathak },
title = { Design of Input Vector Monitoring Concurrent BIST based Architecture for 4-Bit Multiplier },
journal = { International Journal of Computer Applications },
issue_date = { Nov 2016 },
volume = { 153 },
number = { 5 },
month = { Nov },
year = { 2016 },
issn = { 0975-8887 },
pages = { 19-24 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume153/number5/26399-2016912055/ },
doi = { 10.5120/ijca2016912055 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-06T23:58:19.606016+05:30
%A Vinay Kumar Pathak
%A Vinod Kumar Pathak
%T Design of Input Vector Monitoring Concurrent BIST based Architecture for 4-Bit Multiplier
%J International Journal of Computer Applications
%@ 0975-8887
%V 153
%N 5
%P 19-24
%D 2016
%I Foundation of Computer Science (FCS), NY, USA
Abstract

Input vector monitoring in associate with the BIST testing schemes perform testing during the normal operation of the taken circuit without imposing the circuit to be set in offline to perform the test.Testing should authenticate correctness of design and the test procedure. When a new chip is designed and fabricated for the first time, the testing may even take place in the design laboratory rather than in a factory and it frequently needs the participation of the design engineer. IVM-BIST is the best method to perform testing even in offline mode. The proposed method usually used by designers of the systems to check the corrected data received or not. So the fabricated chips first tested before it received by the customer to ensure the quality of the output. This is also known as acceptance testing (or inspection testing) and is conducted either by the user or for the user by some independent testing house. While testing, a part of the circuit (having the fault) is replaced with a corresponding redundant circuit part (by re-adjusting connections), in case any fault is found. BIST is testing a circuit every time before they startup. This paper presents central concepts of testing of VLSI circuits by BIST.

References
  1. Ioannis Voyiatzis, and Costas Efstathiou, “Input Vector Monitoring Concurrent BIST Architecture Using SRAM Cells” IEEE Transaction on very large scale integration system, Vol. 22, NO. 7, pp.1625-1629, July 2014.
  2. Ioannis Voyiatzis, and Antonis Paschalis, “A Concurrent BIST Architecture based on a Self-Testing RAM”, IEEE Transaction on reliability, Vol. 54, NO. 1, pp. 69-78 March 2005.
  3. Philemon Daniel, and Rajeevan Chandel, “Reconfigurable Test Architecture for Online Concurrent Fault Detection Diagnosis and Repair”, International Journal of Design, Analysis And Tools For Integrated Circuit And System, And System, Vol. 3, No. 1, March2012.
  4. M. Malarvizhi, M. Saravanan, and V. Rajendhiran, “Online BIST Architecture using SRAM Cells”, International Journal of Innovative Research & Development, Vol.3, No. 11, pp.315-321 November 2014.
  5. B. Divyapreethi and T. Karthik, “Input Vector Monitoring Concurrent BIST Architecture using Modified SRAM Cells”, ARPN Journal of Engineering and Applied Sciences, Vol. 10, No. 9, pp.4042-4046, May 2015.
  6. S.Abirami, Nikitha.S.Paulin, and S.Prabu Venkteshwaran, “A Concurrent BIST Architecture for input vector monitoring”, International conference on Science, Technology and Management, pp.1411-1488,1 February 2015.
  7. Morasaguru Rajesh Sandeep Kumar.K, and Abdul Rahim, “A Novel Architecture for High Latency BIST using Window Vectors and SRAM Cells”, International Journal of Advance Research Foundation, Vol. 2, No. 7, PP. 32-36 July 2015.
  8. J.Rhinose Fathima, and Dr. R.Vijayabhasker, ‘’Monitoring of Input Vector with Modified BIST”, International Journal of Advanced Research Trends in Engineering and Technology, Vol. 2, No. 1,pp.7-13 January 2015.
  9. Renuka , and Rajendra Kumar , “BIST Technique based on Three Weight Pattern Generation”, International journal of engineering research and science & Technology, Vol.1, No.1, pp.303-306, March 2015.
  10. V.Lalithamani, and R.Mythili, “A CAM Cell based concurrent BIST Architecture”, International journal of engineering research and science & Technology, pp.30-35, March 2015.
  11. H.Sribhuvaneshwari, and S.Selvi, “R112015 IJETCSE - Design of Enhanced BIST Architecture for Input Vector Monitoring” International Journal of Emerging Technology in Computer Science & Electronic, Vol.12, No.4 –February 2015.
  12. DineshKumar, and M.P.Nirmala, “Effective BIST Architecture to Reduce Hardware overhead in digital circuits”, International Journal of Innovative Science, Engineering & Technology, Vol. 2, No.4, pp.862-865, April 2015.
  13. Sheik Husseni, and Nadakuduru Dharmachari, “Design and Implementation of Online BIST Architecture using SRAM Cells”, International hournal of Magazine of Engineering, Technology Management and Research, Vol.2 ,No. 12 pp.328-332,December 2015.
  14. Manchikanti Divyasree, Nalika Aravind, and Dr.P.Ram Mohan Rao, “Implementation of Optimized Reconfigurable Built in Self Repair Scheme for RAMs in SOCs”, International hournal of Magazine of Engineering, Technology Management and Research, Vol.2 ,No. 6 , pp.131-137, June 2015.
  15. S.Manikandan, T.Karthik, and G.Arun Francis, “Vector Monitoring Concurrent BIST Architecture using Modified SRAM Cells”, International journal of scince and advance research in technology, Vol. 1 No.9 ,pp.14-17, Sep 2015.
  16. Selvamani, and Amanda, “BIST Technique based on a Three Weight Pattern Generation”, International Journal for Scientific Research & Development, Vol. 3, No.04, pp.822-825, June 2015.
  17. P. Shyamala Bharathi, and Dr. A. Kaleel Rahuman, “R17-2015 IJSRD - High Performance Scalable Input Vector Monitoring Concurrent BIST Architecture”, International Journal for Scientific Research & Development, Vol. 3, No.02, 2015.
  18. S.Abirami, Nikitha.S.Paulin, and S.Prabu Venkteshwaran, “A Concurrent BIST Architecture for Online Input Vector Monitoring”, International Journal of Science Technology & Management, Volume No.04, Special Issue No.01, pp. 297-303 February 2015.
  19. S.Gurunagalakshmi, and S. Ravanaraja, “Analysis of Input Vector Monitoring Concurrent Built in self Repair and Diagnosis”, International Journal for Trends in Engineering & Technology, Vol.4, No. 1, pp.99-103, April 2015.
  20. K. Keerthika, and Dr. Amos H. jeeva oli, “Online and Offline Testing of C-BIST using SRAM”, IOSR Journal of VLSI and Signal Processing, Volume 5, No. 1, , pp.50-53, February 2015.
Index Terms

Computer Science
Information Sciences

Keywords

Built-in self-test Design for testability Error Detection Input Vector Monitoring Off-Line Testing On-Line Testing Pre-Computed Test Set Self Testing.

Powered by PhDFocusTM