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Introduction to Reversible Logic and Mathematical Derivation for V and V+ Gates
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 153 - Number 5 |
| Year of Publication: 2016 |
| Authors: Amandeep Singh Bhandari, Priya Sharma |
10.5120/ijca2016912054
|
Amandeep Singh Bhandari, Priya Sharma . Introduction to Reversible Logic and Mathematical Derivation for V and V+ Gates. International Journal of Computer Applications. 153, 5 ( Nov 2016), 14-18. DOI=10.5120/ijca2016912054
Abstract
Our computing era has been working long to get a solution for the problem of power dissipation in conventional digital circuitry. Towards this approach, reversible logic has received a significant attention in recent past. Power dissipation occurs due to the loss of information carrying bits during circuit simulation which consequently deteriorates the system performance. Reversible logic allows us to determine the outputs from the inputs and also the inputs can be appropriately recovered from the outputs by using one-to-one mapping. This results in reduced bit loss leading to reduced power dissipation. Reversible logic has been a research paradigm in the field of low-power CMOS, nanotechnology etc. This paper gives a brief description of few reversible logic gates and describes a mathematical derivation to verify how V and V+ gates are square root of NOT gate and Hermitian conjugate of V gate respectively, by using matrix manipulations.
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- Sukhjeet Kaur and Amandeep Singh Bhandari, “Design and Performance Analysis of Encoders using Reversible logic gates”, International Conference on Advancements in Engineering and Technology (ICAET 2015).
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- Santosh Rani and Amandeep Singh Bhandari, “Design and Performance Analysis of Encoders using Reversible logic gates”, Int. Journal of Scientific & Engineering Research (IJSER), Volume 6, Issue 6, June-2015, pp 333-339.
- Manjinder Pal Singh, Er. Birinderjit Singh and Amandeep Singh Bhandari, “Performance Analysis of Low Power Decoders Using Reversible Computing”, International Journal of Research (IJR), e-ISSN: 2348-6848, p- ISSN: 2348-795X Volume 2, Issue 11, November 2015, pp 253-260.
- Navsudeep Kaur, Mr. Amandeep Singh, “Design and Performance Analysis of low PowerReversible Multipliers”, International Journal of Engineering Trends and Technology (IJETT) – Volume 38 Number 5, 2016, pp 261-267.
- Ankush, Amandeep Singh Bhandari, “Design & Performance Analysis of Low Power Reversible Residue Adder”, Int. Journal of Hybrid Information Technology, Volume 9, Issue 9, 2016, pp 93-102.
- Ankush, 2Amandeep Singh Bhandari, “Design & Performance Analysis of Low Power Reversible Carry Skip Adder”, IOSR Journal of VLSI and Signal Processing (IOSR-JVSP) Volume 6, Issue 4
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