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Robust Design of a Dual Edge Triggered Flip Flop at Low Power for High Speed Applications
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 151 - Number 11 |
| Year of Publication: 2016 |
| Authors: Akanchha Rusia, Soumitra S. Pande |
10.5120/ijca2016911930
|
Akanchha Rusia, Soumitra S. Pande . Robust Design of a Dual Edge Triggered Flip Flop at Low Power for High Speed Applications. International Journal of Computer Applications. 151, 11 ( Oct 2016), 1-4. DOI=10.5120/ijca2016911930
Abstract
The logic construction of a double-edge-triggered (DET) flip-flop, which can receive input signal at two levels of the clock, is analyzed and a new circuit design of CMOS DET flip-flop is proposed. Simulation using SPICE and a 1 micron technology shows that this DET flip-flop has ideal logic functionality, a simpler structure, lower delay time and higher maximum data rate compared to other existing CMOS DET flip flops. By simulating and comparing the proposed DET flip-flop with the other designs present, it is shown that the proposed DET flip-flop reduces power dissipation while keeping the same date rate and can be used for high speed applications.
References
- W.M. Chung, T. Lo, and M. Sachdev, “A comparative analysis of low-power low voltage dual-edge-triggered flip-flops," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2014 (accepted).
- A.G.M. Strollo and D. De Caro, “Low Power Flip-Flop with Clock Gating on Master and Slave Latches," Electronics Letters, vol. 31, no. 4, pp. 294-0295, February 2012
- A. Gago, R. Escano, and J.A. Hidalgo, “Reduced Implementation of D-type DET Flip-Flops," IEEE J. of Solid-State Circuits, pp. 400-442, March 2011.
- R.P. Llopis and M. Sachdev, “Low Power, Testable Dual Edge Triggered Flip-Flops," 1996 International Symposium on Low Power Electronics and Design, pp. 341-345, 2011.
- M. Pedram, Q. Wu, and X. Wu, “A New Design of Double Edge Triggered FlipFlops," 1998 Proceedings of the Asian and South Pacific Design Automation Conference (ASPDAC'98), pp. 417-421, 1998.
- A.G.M. Strollo, E. Napoli, and C. Cimino, “Low Power Double Edge-Triggered FlipFlop Using One Latch," Electronics Letters, vol. 35, no. 3, pp. 187-188, 1999.
- J. Tschanz, S. Narendra, Z. Chen, S. Borkar, and M. Sachdev, “Comparative Delay and Energy of Single Edge-Triggered & Dual Edge-Triggered Pulsed Flip-Flops for High-Performance Microprocessors," 2001 Symposium on VLSI Circuits, Digest of Technical Papers., pp. 217-218, 2010.
- T.A. Johnson and I.S. Kourtev, “A Single Latch, High Speed Double-Edge Triggered Flip-Flop (DETFF)," The 8th IEEE International Conference on Electronics, Circuits and Systems, 2001, vol. 1, pp. 189-192, 2001.
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