CFP last date
20 December 2024
Reseach Article

Comparison Study of DIT and DIF Radix-2 FFT Algorithm

by Ranbeer Rathore, Navneet Kaur
International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 150 - Number 7
Year of Publication: 2016
Authors: Ranbeer Rathore, Navneet Kaur
10.5120/ijca2016911565

Ranbeer Rathore, Navneet Kaur . Comparison Study of DIT and DIF Radix-2 FFT Algorithm. International Journal of Computer Applications. 150, 7 ( Sep 2016), 25-28. DOI=10.5120/ijca2016911565

@article{ 10.5120/ijca2016911565,
author = { Ranbeer Rathore, Navneet Kaur },
title = { Comparison Study of DIT and DIF Radix-2 FFT Algorithm },
journal = { International Journal of Computer Applications },
issue_date = { Sep 2016 },
volume = { 150 },
number = { 7 },
month = { Sep },
year = { 2016 },
issn = { 0975-8887 },
pages = { 25-28 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume150/number7/26106-2016911565/ },
doi = { 10.5120/ijca2016911565 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-06T23:55:19.478054+05:30
%A Ranbeer Rathore
%A Navneet Kaur
%T Comparison Study of DIT and DIF Radix-2 FFT Algorithm
%J International Journal of Computer Applications
%@ 0975-8887
%V 150
%N 7
%P 25-28
%D 2016
%I Foundation of Computer Science (FCS), NY, USA
Abstract

The fast fourier transform (FFT) is an important technique for image compression, digital signal processing and communication especially for application in multiple input multiple output OFDM system. The fast fourier transform are good algorithm and computed discrete fourier transform (DFT). In this paper, the comparison study of various FFT algorithm and compare all them. FFT algorithm is divided into two part i.e. decimation in time (DIT) and decimation in frequency (DIF). In DIT algorithm firstly computed multiplier then adder but in DIF firstly computed adder then multiplier. In this paper we study of different types of multiplier i.e. array multiplier; sing multiplier (Baugh Wooley) and complex multiplier. In proposed complex multiplier is consuming three multipliers. In further work in my dissertation in design to 8-point, 16-point, 32-point, 64-point and 128-point radix FFT algorithm in different multiplier.

References
  1. Pramod Kumar Mehe, Basant Kumar Mohanty, Sujit Kumar Patel, Soumya Ganguly, and Thambipillai Srikanthan, “Efficient VLSI Architecture for Decimation-in-Time Fast Fourier Transform of Real-Valued Data”, IEEE Transactions on Circuits And Systems—I: Regular Papers, Vol. 62 , No. 12, December 2015.
  2. Himanshu Thapaliyal and M.B Srinivas, “VLSI Implementation of RSA Encryption System Using Ancient Indian Vedic Mathematics”, Center for VLSI and Embedded System Technologies, International Institute of Information Technology Hyderabad, India 2014.
  3. M. Ayinala, Y. Lao, and K. K. Parhi, “An in-place FFT architecture for real-valued signals,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 60, no. 10, pp. 652–656, Oct. 2013.
  4. S. S. Kerur, Prakash Narchi, Jayashree C N, Harish M Kittur and Girish V A, “Implementation of Vedic multiplier for Digital Signal Processing”, International Conference on VLSI, Communication & Instrumentation (ICVCI) 2011, Proceedings published by International Joural of Computer Applications® (IJCA), pp.1-6.
  5. Jagadguru Swami Sri Bharati Krishna Tirthaji Maharaja, “Vedic Mathematics: Sixteen simple Mathematical Formulae from the Veda”, Delhi (2011).
  6. D. Tsonev, S. Sinanovic and H. Haas, “Enhanced subcarrier index modulation (SIM) OFDM,” in IEEE Global Communications Conference (IEEE GLOBECOM 2011), 5–9Dec. 2011.
  7. Charles. Roth Jr., “Digital Systems Design using VHDL”, Thomson Brooks/Cole, 7th reprint, 2005.
  8. S. S. Kerur, Prakash Narchi, Jayashree C N, Harish M Kittur and Girish V A, “Implementation of Vedic multiplier for Digital Signal Processing”, International Conference on VLSI, Communication & Instrumentation (ICVCI) 2011, Proceedings published by International Joural of Computer Applications® (IJCA), pp.1-6.
  9. Himanshu Thapaliyal and M.B Srinivas, “VLSI Implementation of RSA Encryption System Using Ancient Indian Vedic Mathematics”, Center for VLSI and Embedded System Technologies, International Institute of Information Technology Hyderabad, India.
  10. Jagadguru Swami Sri Bharati Krishna Tirthaji Maharaja, “Vedic Mathematics: Sixteen simple Mathematical Formulae from the Veda”, Delhi (2011).
  11. Harpreet Singh Dhillon and Abhijit Mitra, “A Reduced-bit Multiplication Algorithm for Digital Arithmetic”, International Journal of Computational and Mathematical Sciences, Febrauary 2008, pp.64-69.
  12. Sumit Vaidya and Depak Dandekar. “Delay-power performance comparison of multipliers in VLSI circuit design”. International Journal of Computer Networks & Communications (IJCNC), Vol.2, No.4, July 2010.
  13. Pramod Kumar Mehe, Basant Kumar Mohanty, Sujit Kumar Patel, Soumya Ganguly, and Thambipillai Srikanthan, “Efficient VLSI Architecture for Decimation-in-Time Fast Fourier Transform of Real-Valued Data”, IEEE Transactions on Circuits And Systems—I: Regular Papers, Vol. 62, No. 12, December 2015.
  14. M. Ayinala, Y. Lao, and K. K. Parhi, “An in-place FFT architecture for real-valued signals,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 60, no. 10, pp. 652–656, Oct. 2013.
  15. Shashank Mittal, Md. Zafar Ali Khan and M.B. Srinivas, “Area Efficient High Speed Architecture of Bruun’s FFT for Software Defined Radio”, 1930-529X/07/$25.00 © 2007 IEEE.
  16. B. G. Jo and M. H. Sunwoo, “New continuous-flow mixed-radix (CFMR) FFT processor using novel in-place strategy,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 52, no. 5, pp. 911–919, May 2005.
Index Terms

Computer Science
Information Sciences

Keywords

FFT Decimation in Time Decimation in Frequency real Value data