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FPGA Implementation of Torus NOC Architecture
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 150 - Number 3 |
| Year of Publication: 2016 |
| Authors: Ashish Valuskar, Madhu Shandilya, Arvind Rajawat |
10.5120/ijca2016911472
|
Ashish Valuskar, Madhu Shandilya, Arvind Rajawat . FPGA Implementation of Torus NOC Architecture. International Journal of Computer Applications. 150, 3 ( Sep 2016), 9-10. DOI=10.5120/ijca2016911472
Abstract
Network on Chip architectures (NoC) are considered the next generations interconnect systems for multiprocessor systems-on-chip. Selection of the network architecture and mapping of IP nodes onto the NoC topology are two important research topics. Most of the researchers implement the noc architectures either using virtual channel routers or using simulators, but in this paper we implement well known interconnect system specifically 3x3 torus noc architecture using store and forward technique based router architecture in VHDL.
References
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