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Design Optimization and Performance Analysis of Inverter Circuit using DG-MOSFET at Sub 32nm

by Anita Nalawade, Subha Subramaniam
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International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 149 - Number 12
Year of Publication: 2016
Authors: Anita Nalawade, Subha Subramaniam
10.5120/ijca2016911639

Anita Nalawade, Subha Subramaniam . Design Optimization and Performance Analysis of Inverter Circuit using DG-MOSFET at Sub 32nm. International Journal of Computer Applications. 149, 12 ( Sep 2016), 5-8. DOI=10.5120/ijca2016911639

@article{ 10.5120/ijca2016911639,
author = { Anita Nalawade, Subha Subramaniam },
title = { Design Optimization and Performance Analysis of Inverter Circuit using DG-MOSFET at Sub 32nm },
journal = { International Journal of Computer Applications },
issue_date = { Sep 2016 },
volume = { 149 },
number = { 12 },
month = { Sep },
year = { 2016 },
issn = { 0975-8887 },
pages = { 5-8 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume149/number12/26047-2016911639/ },
doi = { 10.5120/ijca2016911639 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-06T23:54:32.850147+05:30
%A Anita Nalawade
%A Subha Subramaniam
%T Design Optimization and Performance Analysis of Inverter Circuit using DG-MOSFET at Sub 32nm
%J International Journal of Computer Applications
%@ 0975-8887
%V 149
%N 12
%P 5-8
%D 2016
%I Foundation of Computer Science (FCS), NY, USA
Abstract

In this paper, the design and performance of inverter circuit using Double gate MOSFET at 32nm Sub-micron CMOS technology has presented. The DG-MOSFET has a potential to overcome the problem of SCE. DG-MOSFET has been used for improvement in performance and reducing power dissipation. In this work, the propagation delay and dynamic power dissipation is observed for inverter circuit. Also the analysis of DG-MOSFET has been done using nanohub tool.

References
  1. Ravindra Singh Kushwah, Shyam Akashe “Design and Analysis of Tunable Analog Circuit Using Double Gate MOSFET at 45nm CMOS Technology” 2013 3rd IEEE International Advance Computing Conference (IACC).
  2. Marcus Weis, Andrzej Pfitzner, Dominik Kasprowicz , Rainer Emling, Wojciech Maly, Doris Schmitt-Landsiedel “Adder Circuits With Transistors Using In dependently Controlled Gates”. 978-1-4244-3828-0/09/$25.00 ©2009 IEEE
  3. Nanohub.org.in
  4. Subha Subramaniam, Sangeeta.M.Joshi, R.N.Awale, “Suitability of High-k GateDielectrics on the Device Performance and Scalability of Nanoscale Double Gate FinFETs Simulation Study”, Journal of Electron Devices (JED), FRANCE, Vol.18,2013,pp.1582-1586.
  5. Subha Subramaniam, Sangeeta.M.Joshi, R.N.Awale, “Design and Analysis of Novel Complementary Metal Oxide Semiconductor Inverter Circuit with integration of N-InGaAs and P-SiGe Vertical Nanowire Transistors”, Advanced Science, Engineering and Medicine, Volume 8, Number 3, March 2016, pp.175-180(6).
Index Terms

Computer Science
Information Sciences

Keywords

Short channel effect Drain induced barrier lowering single gate MOSFET Double gate MOSFET

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