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Techniques for the Design of High Speed and Low Power MAC Unit: A Sate-of-the-art Review

by Anu, Prachi Chaudhary, Pawan Kumar Dahiya
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International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 148 - Number 13
Year of Publication: 2016
Authors: Anu, Prachi Chaudhary, Pawan Kumar Dahiya
10.5120/ijca2016911245

Anu, Prachi Chaudhary, Pawan Kumar Dahiya . Techniques for the Design of High Speed and Low Power MAC Unit: A Sate-of-the-art Review. International Journal of Computer Applications. 148, 13 ( Aug 2016), 22-25. DOI=10.5120/ijca2016911245

@article{ 10.5120/ijca2016911245,
author = { Anu, Prachi Chaudhary, Pawan Kumar Dahiya },
title = { Techniques for the Design of High Speed and Low Power MAC Unit: A Sate-of-the-art Review },
journal = { International Journal of Computer Applications },
issue_date = { Aug 2016 },
volume = { 148 },
number = { 13 },
month = { Aug },
year = { 2016 },
issn = { 0975-8887 },
pages = { 22-25 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume148/number13/25818-2016911245/ },
doi = { 10.5120/ijca2016911245 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-06T23:53:17.485401+05:30
%A Anu
%A Prachi Chaudhary
%A Pawan Kumar Dahiya
%T Techniques for the Design of High Speed and Low Power MAC Unit: A Sate-of-the-art Review
%J International Journal of Computer Applications
%@ 0975-8887
%V 148
%N 13
%P 22-25
%D 2016
%I Foundation of Computer Science (FCS), NY, USA
Abstract

The multiplication operation is used in many parts of a digital system or digital computer, usually in signal processing, video/graphics and scientific computation. With advances in technology, various techniques have been developed to design multipliers, which offer high speed, low power consumption and lesser area. Thus making them suitable for various high speeds, low power compact VLSI implementations. These three parameters i.e. power, area and speed are always traded off. In this paper, different techniques used for efficient operations resulting in high speed and low power consumption are discussed. Such as parallelism, pipelining, modified booth algorithm (MBA), spurious power suppression technique (SPST), block enabling technique.

References
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Index Terms

Computer Science
Information Sciences

Keywords

Multiply and Accumulate (MAC) Modified Booth Algorithm (MBA) parallel modified booth multiplier Spurious Power Suppression Technique (SPST) block enabling technique.

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