The week's pick
Reseach Article
Techniques for the Design of High Speed and Low Power MAC Unit: A Sate-of-the-art Review
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 148 - Number 13 |
| Year of Publication: 2016 |
| Authors: Anu, Prachi Chaudhary, Pawan Kumar Dahiya |
10.5120/ijca2016911245
|
Anu, Prachi Chaudhary, Pawan Kumar Dahiya . Techniques for the Design of High Speed and Low Power MAC Unit: A Sate-of-the-art Review. International Journal of Computer Applications. 148, 13 ( Aug 2016), 22-25. DOI=10.5120/ijca2016911245
Abstract
The multiplication operation is used in many parts of a digital system or digital computer, usually in signal processing, video/graphics and scientific computation. With advances in technology, various techniques have been developed to design multipliers, which offer high speed, low power consumption and lesser area. Thus making them suitable for various high speeds, low power compact VLSI implementations. These three parameters i.e. power, area and speed are always traded off. In this paper, different techniques used for efficient operations resulting in high speed and low power consumption are discussed. Such as parallelism, pipelining, modified booth algorithm (MBA), spurious power suppression technique (SPST), block enabling technique.
References
- R. Mohanapriya and K. Rajesh, “A Modified Architecture Of Multiplier And Accumulator Using Spurious Power Suppression Technique,” International Journal of Students’ Research in Technology & Management Vol. 3, No. 2, ISSN 2321-2543, pp. 258-263, February 2015.
- Syed Anwar Ahmed and MD Salahuddin, “Design of High Speed Architecture of Parallel MAC Based On Radix-2 MBA,” Syed Anwar Ahmed et al. Int. Journal of Engineering Research and Applications www.ijera.com ISSN : 2248-9622, Vol. 4, Issue 5( Version 7), May 2014, pp. 56-61.
- Narendra C.P and Dr. K.M. Ravi Kumar, “Computing (Low Power MAC Architecture for DSP Applications,” Proceedings of International Conference on Circuits, Communication, Control and Computing (I4C 2014).
- K. Jeswanth Singh and B. Vamsi Krishna, “Design and Implementation of Modified Booth Encoder Multiplier using Carry Select Adder,” International Journal of Recent Technology and Engineering (IJRTE), Volume-3 Issue-5, November 2014.
- Aishwarya. E. V. and Aarthy.M, “Design of High Speed Pipelined Merged MAC Using Radix-4 MBA and Carry Select Adder,” International Journal of Engineering Research & Technology (IJERT), pp. 2278-0181, Vol. 3, Issue 4, April – 2014.
- M. D. Riazullah and K. Kishore Kumar, “VLSI Implementation of Low Power Multiplier and Accumulator Unit using SPST,” International Journal of Science, Engineering and Technology Research (IJSETR), Volume 3, Issue 12, December 2014.
- Soniya and Suresh Kumar, “A Review of Different Type of Multipliers and Multiplier-Accumulator Unit,” International Journal of Emerging Trends & Technology in Computer Science (IJETTCS) Volume 2, Issue 4, July – August 2013, pp. 2278-6856.
- Naveen Kumar, Manu Bansal and Amandeep Kaur, “Speed Power and Area Efficent VLSI Architectures of Multiplier and Accumulator”, International Journal of Scientific & Engineering Research Volume 4, Issue 1, January-2013, pp. 2229-5518.
- Avisek Sen, Partha Mitra and Debarshi Datta, “Low Power MAC Unit for DSP Processor,” International Journal of Recent Technology and Engineering (IJRTE), pp. 2277-3878, Volume-1, Issue-6, January- 2013.
- Sukhmeet Kaur, Suman and Manpreet Signh Manna, “Implementation of Modified Booth Algorithm (Radix 4) and its Comparison with Booth Algorithm (Radix-2),” Advance in Electronic and Electric Engineering, Volume 3, Number 6 (2013), pp. 683-690.
- Deepika Setia and Charu Madhu, “Novel Architecture of High Speed Parallel MAC using Carry Select Adder,” International Journal of Computer Applications (0975 – 8887), Vol. 74, No.1, July -2013.
- H. S. Krishnaprasad Puttam, P. Sivadurga Rao & N. V. G. Prasad, “Implementation of Low Power and High Speed Multiplier-Accumulator Using SPST Adder and Verilog,” International Journal of Modern Engineering Research (IJMER), Vol. 2, Issue 5, Sep.-Oct.- 2012, pp. 3390-3397.
- Iffat Fatima ,“ Analysis of Multipliers in VLSI” Journal of Global Research in Computer Science, Journal of Global Research in Computer Science, Volume 3, No. 11, November 2012.
- S. Anitha, M. Vidya and D. Mahesh Varma, “Design of Parallel MAC Based On Radix-4 & Radix-8,” International Journal of Research in Computer and Communication technology, (IJRCCT), Vol. 1, Issue 7, December-2012, pp. 2278-5841.
- Young-Ho Seo and Dong-Wook Kim,“A New VLSI Architecture of Parallel Multiplier–Accumulator Based on Radix-2 Modified Booth Algorithm,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 18, No. 2, February- 2010.
- Fayez Elguibaly, “A Fast Parallel Multiplier-Accumulator Using theModified Booth Algorithm,” IEEE Transactions on Circuits And Systems—Ii: Analog And Digital Signal Processing, Vol. 47, No. 9, September 2000.
- Shankey Goel and R.K. Sharma, “Parallel MAC Based On Radix-4 & Radix-8 Booth Encodings,” International Journal of Engineering Science and Technology (IJEST).
- Priya Stalin, Anuradha, K. Ranjithkumar, N. Vaishnav, D Vigneswara and S. T. Santhosh, “High Speed Multiplier With Pipelining,” International Journal of VLSI and Embedded Systems (IJVES).
- K. Srishylam, Prof. Syed Amjad Ali and M. Praveena, “ Implementation of Hybrid CSA, Modified Booth Algorithm and Transient power Minimization techniques in DSP/Multimedia Applications,” International Journal of Engineering Research and Applications (IJERA).
- Koc, C.K., “RSA Hardware Implementation”, RSA Laboratories, RSA Data Security, Inc. 1996.
Index Terms
Keywords