The week's pick
Reseach Article
Performance Analysis of Different 8x8 Bit CMOS Multiplier using 65nm Technology
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 148 - Number 13 |
| Year of Publication: 2016 |
| Authors: Sona Rani, Ajay Kumar, Vikas Singla, Rakesh Singla |
10.5120/ijca2016911049
|
Sona Rani, Ajay Kumar, Vikas Singla, Rakesh Singla . Performance Analysis of Different 8x8 Bit CMOS Multiplier using 65nm Technology. International Journal of Computer Applications. 148, 13 ( Aug 2016), 1-6. DOI=10.5120/ijca2016911049
Abstract
In this paper different low power 8x8 bit multipliers which are implemented with Tanner Tool v13.0 at 250MHz and 500MHz frequency with 65nm technology which is having a supply voltage 1.0v. There are different CMOS multiplier circuits are analyzed which are Array multiplier, Wallace tree multiplier, Row bypass Braun multiplier, Column bypass Braun multiplier, Row and Column bypass Braun multiplier and these multiplier are realized using bridge style full adder. All these multipliers are compared in terms of delay, power dissipation and power delay product. Simulation results show that the Array multiplier and Wallace tree multiplier using bridge style adder has less power delay product and is faster as compared to other CMOS multipliers.
References
- Sung-Mo Kang, Yusuf Leblebici., "CMOS Digital Integrated Circuits" Tata McGraw-Hill, 2003.
- J.Rabaey, “Digital Integrated Circuits (A Design Perspective)”, Prentice-Hall, Englewood Cliffs, NJ, 1996.
- Kamran, Eshrcighian, douglous, A hucknell, Sholeh eshraghia “ Essential of VlSI circuits and systems”, 2013.
- M.B.Damle, Dr.S.S Limaye, M.G.Sonwani, “ Comparative analysis of different types of full adder circuits”, Vol.11, Issue 3, 2013.
- Neil Weste, A. Eshragian, "Principal of CMOS VLSI: system perceptive", Pearson/Addision Wesley publisher, 2005.
- P.R.Panda, “Basic low power digital design” springer science and business media, 2010.
- Sumit Vaidya, Dandekar. D, "Delay-power performance comparison of multipliers in VLSI circuit design", International Journal of Computer Networks & Communications (IJCNC), Vol.2, No.4, 2010.
- Yuke Wang, Yingtao Jiang, "On Area-Efficient Low Power Array Multipliers", 8th IEEE International Conference on Electronics, Circuits and Systems, pp 1429 - 1432, vol. 3, 2-5 Sep 2001.
- C.S. Wallace, "A suggestion for a fast multiplier", in IEEE Trans. On Electronic Computers, vol. EC-13, pp. 14-17, 1964.
- Yin-Tsung Hwang, Jin-Fa Lin, Ming-Hwa Sheu and Chia-Jen Sheu, “low power multipliers using enhanced row bypassing schemes”, department of electronic engineering, National Yunlin University of science & technology, Touliu, Yunlin, Taiwan, IEEE, pp.136-140, 2007.
- M. C. Wen, S. J. Wang and Y. M. Lin, “Low power parallel multiplier with column bypassing” , IEEE International Symposium on Circuits and Systems, pp.1638-1641, 2005.
- Jin-Tai Yan and Zhi-Wei Chen, "Low-power multiplier design with row and column bypassing", department of computer science and information engineering, chung-hua university, hsinchu, taiwan, R.O.C, IEEE, pp.227-230, 2009.
- Mohammad Reza Bagheri, "Ultra Low Power Sub-threshold Bridge Style Adder in Nanometer Technologies", Canadian Journal on Electrical and Electronics Engineering, Vol. 2, No. 7, 2011.
Index Terms
Keywords