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Area-Delay Efficient Flipping 2-d DWT Structure using PEB Booth Multiplier

by Vikas Tiwari, B. K. Mohanty
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International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 146 - Number 13
Year of Publication: 2016
Authors: Vikas Tiwari, B. K. Mohanty
10.5120/ijca2016910929

Vikas Tiwari, B. K. Mohanty . Area-Delay Efficient Flipping 2-d DWT Structure using PEB Booth Multiplier. International Journal of Computer Applications. 146, 13 ( Jul 2016), 36-38. DOI=10.5120/ijca2016910929

@article{ 10.5120/ijca2016910929,
author = { Vikas Tiwari, B. K. Mohanty },
title = { Area-Delay Efficient Flipping 2-d DWT Structure using PEB Booth Multiplier },
journal = { International Journal of Computer Applications },
issue_date = { Jul 2016 },
volume = { 146 },
number = { 13 },
month = { Jul },
year = { 2016 },
issn = { 0975-8887 },
pages = { 36-38 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume146/number13/25461-2016910929/ },
doi = { 10.5120/ijca2016910929 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-06T23:50:24.068806+05:30
%A Vikas Tiwari
%A B. K. Mohanty
%T Area-Delay Efficient Flipping 2-d DWT Structure using PEB Booth Multiplier
%J International Journal of Computer Applications
%@ 0975-8887
%V 146
%N 13
%P 36-38
%D 2016
%I Foundation of Computer Science (FCS), NY, USA
Abstract

In this paper, an area-delay efficient structure for two-dimensional discrete wavelet transform (2-D DWT) is proposed. The proposed structure has a small cycle period, and offer high throughput compared to the existing structures due to its efficient arithmetic unit (AU). The flipping scheme and efficient probability estimated biased (PEB) Booth multiplier provide efficient area-delay product (ADP) and energy per image (EPI) DWT computation for output of the filter. Compared with existing flipping-based structure, the proposed AU based flipping structures, involve 4.5 times as little as ADP for block-sizes 16. The flipping scheme offer ADP efficient large block size structure due to efficient arithmetic computation unit .

References
  1. Taubman D. and A. Zakhor, “Multirate 3-d subband coding of video,” IEEE Trans. Image Processing, vol. 3, pp. 572–588.Sept (1994).
  2. Kronland-Martinet R., Morlet J., Grossmann A. "Analysis of sound patterns through wavelet transforms" Int. Journal of Pattern Recognition and Artificial Intelligence, vol. 1, pp.273-302, (1987).
  3. Stoksik M. A., R.G. Lane and D.T. Nguyen “Accurate synthesis of fractional Brownian motion using wavelets” Electronics Letters, IET Volume:30 ,  Issue: 5 (1994).
  4. Senhadji, L., Carrault, G. and Bellanguer, J. J. , “Interictal EEG spike detection: A new framework based on the wavelet transforms,” in Proc. IEEE-SP International Symposium on Time-Frequency and Time-Scale Analysis, pp. 548–551 (1994).
  5. Dai, Q., Chen, X. and Lin, C. , “A novel VLSI architecture for multidimensional discrete wavelet transform,” IEEE Transactions on Circuits and Systems for Video Technology, vol. 14, no. 8, pp. 1105–1110, (2004).
  6. Vishwanath M., “ The recursive pyramid algorithm for the discrete wavelet transform,” IEEE Trans. Signal Processing, vol. 42, no. 3, pp.673-677, Mar. (1994).
  7. Wu P. C. and L.-G. Chen, “An efficient architecture for 2-D discrete wavelet transform,” IEEE Trans. Circuits Syst. Video Technol., vol. 11,no. 4, pp. 536–545, (Apr. 2001).
  8. Cheng C-C., C.-T. Huang, C.-Y. Cheng, C.-Jr. Lian, and L.-G. Chen,“On-chip memory optimization scheme for VLSI implementation of line-based 2-D discrete wavelet transform,” IEEE Trans. Circuit Syst.Video Technol., vol. 17, no. 7, pp. 814–822, Jul. (2007).
  9. Zhang, W., Jiang, Z., Gao, Z. and Liu, Y., “An efficient VLSI architectures for lifting-based discrete wavelet transform,” IEEE Transactions on Circuits and Systems–II, Express Briefs, vol. 59, no. 3, pp. 158-162, (2012).
  10. SAED (Synopsys Armenia Educational Department) Library 90nm, www.synopsys.com.
  11. Huang C-T., P.-C. Tseng, and L.-G. Chen, "Analysis and VLSI Architecture for 1-D and 2-D Discrete Wavelet Transform," IEEE Transactions on Signal Processing, vol. 53, no. 4, pp1575-1586, (April 2005).
  12. Mohanty B. K. and Tiwari V. “ Modified PEB formulation for hardware efficient fixed-width Booth multiplier” Springer, CSSP vol 33 issue 12,(Dec. 2014)
Index Terms

Computer Science
Information Sciences

Keywords

Discrete wavelet transforms VLSI architecture Flipping scheme Digital filter.

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