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Area-Delay Efficient Flipping 2-d DWT Structure using PEB Booth Multiplier
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 146 - Number 13 |
| Year of Publication: 2016 |
| Authors: Vikas Tiwari, B. K. Mohanty |
10.5120/ijca2016910929
|
Vikas Tiwari, B. K. Mohanty . Area-Delay Efficient Flipping 2-d DWT Structure using PEB Booth Multiplier. International Journal of Computer Applications. 146, 13 ( Jul 2016), 36-38. DOI=10.5120/ijca2016910929
Abstract
In this paper, an area-delay efficient structure for two-dimensional discrete wavelet transform (2-D DWT) is proposed. The proposed structure has a small cycle period, and offer high throughput compared to the existing structures due to its efficient arithmetic unit (AU). The flipping scheme and efficient probability estimated biased (PEB) Booth multiplier provide efficient area-delay product (ADP) and energy per image (EPI) DWT computation for output of the filter. Compared with existing flipping-based structure, the proposed AU based flipping structures, involve 4.5 times as little as ADP for block-sizes 16. The flipping scheme offer ADP efficient large block size structure due to efficient arithmetic computation unit .
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