CFP last date
20 December 2024
Reseach Article

Design of Low Power and Area Efficient Full Adder using Modified Gate Diffusion Input

by S. Swetha
International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 145 - Number 8
Year of Publication: 2016
Authors: S. Swetha
10.5120/ijca2016910778

S. Swetha . Design of Low Power and Area Efficient Full Adder using Modified Gate Diffusion Input. International Journal of Computer Applications. 145, 8 ( Jul 2016), 45-47. DOI=10.5120/ijca2016910778

@article{ 10.5120/ijca2016910778,
author = { S. Swetha },
title = { Design of Low Power and Area Efficient Full Adder using Modified Gate Diffusion Input },
journal = { International Journal of Computer Applications },
issue_date = { Jul 2016 },
volume = { 145 },
number = { 8 },
month = { Jul },
year = { 2016 },
issn = { 0975-8887 },
pages = { 45-47 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume145/number8/25302-2016910778/ },
doi = { 10.5120/ijca2016910778 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-06T23:48:17.675756+05:30
%A S. Swetha
%T Design of Low Power and Area Efficient Full Adder using Modified Gate Diffusion Input
%J International Journal of Computer Applications
%@ 0975-8887
%V 145
%N 8
%P 45-47
%D 2016
%I Foundation of Computer Science (FCS), NY, USA
Abstract

The low power techniques are becoming more important due to rapid development of portable digital applications; demand for high-speed and low power consumption.GDI (Gate Diffusion Input) is one of the low power and area efficient technique. GDI requires less number of transistors compared to CMOS technology. The basic cell of GDI consists of two transistors where three terminals i.e Gate, Source and Drain considered as inputs. Therefore, it is helpful for low power, delay and area. But the disadvantage of GDI is its output has poor logic swing .This paper presents low power high performance multiplexer based full adder design in CADENCE VIRTUOSO GPDK 45nm Technology.  The power consumption comparison is also made based on CMOS and GDI design technique.

References
  1. Deepali Koppad, Sujatha Hiremath “Low Power 1-Bit Full Adder Circuit Using Modified Gate Diffusion Input (GDI)” conference on First International micro and nano technologies.
  2. R.uma and P.Davachelvan”low power and High Speed Adders in Modified gate Diffusion InputTechnique” Computer Networks & Communications (NetCom).
  3. Anshul Jain, Abul Hassan” Design of Low power multiplexers using different Logics” International Journal ofScience,Technology,and managenment Vol-4.
  4. T. Esther Rani, M. Asha Rani, Dr. Rameshwar rao, “Area Optimized Low Power Arithmetic And Logic Unit” 978-1-4244-8679-3/11/$26.00 ©2011 IEEE.
  5. Deepali Koppad, Sujatha Hiremath “ Low Power Circuits using Modified Gate Diffusion Input (GDI)” internal organization of scientific research Vol-4 Oct-2014.
Index Terms

Computer Science
Information Sciences

Keywords

GDI CMOS Modified GDI Multiplexer Full swing low power consumption.