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Leakage Power Reduction by using Sleep Switches in Domino Logic Circuit Design in DSM Technology
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 145 - Number 7 |
| Year of Publication: 2016 |
| Authors: Kuldeep Patel, Monika Kapoor |
10.5120/ijca2016910589
|
Kuldeep Patel, Monika Kapoor . Leakage Power Reduction by using Sleep Switches in Domino Logic Circuit Design in DSM Technology. International Journal of Computer Applications. 145, 7 ( Jul 2016), 17-21. DOI=10.5120/ijca2016910589
Abstract
Power consumption is hurdle problem face by nanometer CMOS circuit in deep submicron process (DSM) technology. As technology scales down, leakage power significantly increases very rapidly due to high transistor density, reduced voltage and oxide thickness. A new circuit technique based on: “Sleep Switch” is proposed in this paper for reducing the subthreshold and gate oxide leakage currents when circuit is operating in idle and non idle mode in domino circuit design. In this technique a p-type and an n-type leakage controlled sleep transistor are introduced between the pull-up and pull-down network and their gates are controlled by the source of the other. For any combination of input, one of the Sleep transistor will operate near cut off region which increase the resistance path between supply voltage and ground resulting in reduced leakage current. The proposed circuit technique reduces the active power consumption by 14.3% to 44.45% and by 12% to 33% at the low and high die temperature respectively compared to the standard footerless domino logic circuits. During idle mode, 11.64% to 78.39% and 21.2% to 36.19% reduction of leakage current is observed with low and high inputs at 250C and 1100C respectively. Similarly, during non-idle mode 0.94% to 99.3% and 1.57% to 98.58% is observed with low and high inputs at 25oC to 1100C respectively when compared to standard footerless domino logic circuits.
References
- H. Mahmoodi and K. Roy, “Diode-footed domino: A leakage-tolerant high fan-in dynamic circuit design style”, IEEE Transactions on Circuits and Systems-I, vol. 51, no. 3, pp. 495-503, 2004.
- C. C. Wang, C. C. Huang, C. L. Lee and T. W. Cheng, “ A low power high speed 8 bit pipeling CLA design using dual-threshold voltage domino logic”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 16, no. 5,pp. 594-598, 2008.
- F. Frustaci, M. Lanuzza, P. Zicari, S. Perri and P. Corsonello, “ Low-power split data-driven dynamic logic”, IET Circuits Devices and Systems, vol. 3, no. 6, pp. 303-312, 2009.
- I. S. Hwang and A. L. Fishers, “Ultrafast compact 32-bit CMOS adders in multiple-output domino logic”, IEEE Journal of Solid-State Circuits, vol. 24, no. 2, pp. 358-369, 1989.
- V. N. Botello, J. A. Montel and S. Nooshabad, “ High performance low power CMOS dynamic logic for arithmetic circuits”, Microelectronics Journal, vol. 38, pp. 482-488, 2007.
- F. Chaochao, C. Xun, Y. Xiaofei and Z. Minxuan, “An improved high fan-in domino circuit for high performance microprocessor”, Journal of Semiconductor, vol. 29, no. 9, pp. 1740-1744, 2008.
- R. J. Hung and Duncan. G. Elliot, “Clock-logic domino circuits for high speed and energy-efficient microprocessor pipelines”, IEEE Transactions on Circuits and Systems-II, vol. 54, no. 5, pp. 460-464, 2007.
- K. J. Nowka and T. Galambos, “Circuit design techniques for a gigahertz integer microprocessor”, Proceedings of the IEEE International Conference on Computer Design, pp. 11-16, 1998.
- K. Roy, S. Mukhopadhyay and H. Mahmoodi-Meimand, “Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits,” Proceedings of the IEEE, vol. 91, no. 2, pp. 305–327, 2003.
- D. Soudris, C. Piguet and C. Goutis, Designing CMOS Circuits for Low Power, Kluwer Academic Publishers, 2005
- A. P. Chandrakasan, S. Sheng and R. W. Bordersen, “Low-power CMOS digital design,” IEEE Journal of Solid-State Circuits, vol. 27, no. 4, pp. 473- 484, 1992.
- Fang Lu and Henry Samueli, “A High-Speed CMOS Full Adder Cell Using A New Circuit Design Technique Adaptively Biased Pseudo-NMOS Logic,” Proceedings of the IEEE International Conference, pp. 562-565, 1990.
- G. Hoyer, “Locally-clocked dynamic logic”, Proceedings of the Midwest Symposium on Circuits and Systems, pp. 18-21, 1998. 86
- S. Kamthey, T. N. Sharma, R. K. Nagaria and S. Wairya, “A Novel Design for Testability of Multiple Precharged Domino CMOS Circuits”, World Applied Science Journal (WASJ: Special Issue of Computer & IT), IDOSI Publication, vol. 7, pp. 175-181, 2009.
- H. Veendrick, “Short circuit dissipation of static CMOS circuitry and its impact on the design of buffer circuits”, IEEE Journal of Solid-State Circuits, vol. 19, no. 4, pp. 468-473, 1984.
- A. P. Chandrakasan and R. W. Brodersen, “Minimizing power consumption in digital CMOS circuits”, Proceedings of the IEEE Conference, pp. 498–523, April 1995.
- S. Borkar, “Low power design challenges for the decade”, Proceedings of the IEEE/ACM Asia and South Pacific Design Automation Conference, pp. 293-296, June 2001.
- D. Liu and C. Svensson, “Trading speed for low power by choice of supply and threshold voltages”, IEEE Journal of Solid-State Circuits, vol. 28, no. 1, pp. 10-17, 1993.
- R. Gonazales, B. M. Gordon, and M. A. Horowitz, “Supply and threshold voltage scaling for low power CMOS”, IEEE Journal of Solid-State Circuits, vol. 32, no. 8, pp. 1210-1216, 1997.
- A. P. Chandrakasan and R. W. Brodersen, “Minimizing power consumption in digital CMOS circuits”, Proceedings of the IEEE, pp. 498-523, April 1995.
- R. A. Freking, K. Parhi, “Theoretical estimation of power consumption in binary adders”, Proceedings of the ISCAS’98, pp. 453-457, 1998.
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