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Low Power Ring Oscillator at 180nm CMOS Technology
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 144 - Number 8 |
| Year of Publication: 2016 |
| Authors: Aman Shivhare, M. K. Gupta |
10.5120/ijca2016910421
|
Aman Shivhare, M. K. Gupta . Low Power Ring Oscillator at 180nm CMOS Technology. International Journal of Computer Applications. 144, 8 ( Jun 2016), 25-28. DOI=10.5120/ijca2016910421
Abstract
In this paper a low power design for CMOS ring oscillator is proposed and analyzed for power consumption. The proposed design is compared with an existing design. the simulation is done on Cadence virtuoso tool at 180nm CMOS technology and the results are analyzed for power consumption. The proposed ring oscillator circuit uses positive feedback in its inverter based circuit and operate with nine cascading CMOS inverter. The power consumption of the proposed design is reduced by 28.40% at 0.9v and 54.64% at 1v as compared with a previous design.
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