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Minimization of Multiple Value function using Quine Mc-Cluskey Technique

by Prashant S. Wankhade, Gajanan Sarate
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International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 143 - Number 7
Year of Publication: 2016
Authors: Prashant S. Wankhade, Gajanan Sarate
10.5120/ijca2016910257

Prashant S. Wankhade, Gajanan Sarate . Minimization of Multiple Value function using Quine Mc-Cluskey Technique. International Journal of Computer Applications. 143, 7 ( Jun 2016), 29-33. DOI=10.5120/ijca2016910257

@article{ 10.5120/ijca2016910257,
author = { Prashant S. Wankhade, Gajanan Sarate },
title = { Minimization of Multiple Value function using Quine Mc-Cluskey Technique },
journal = { International Journal of Computer Applications },
issue_date = { Jun 2016 },
volume = { 143 },
number = { 7 },
month = { Jun },
year = { 2016 },
issn = { 0975-8887 },
pages = { 29-33 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume143/number7/25090-2016910257/ },
doi = { 10.5120/ijca2016910257 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-06T23:46:24.989418+05:30
%A Prashant S. Wankhade
%A Gajanan Sarate
%T Minimization of Multiple Value function using Quine Mc-Cluskey Technique
%J International Journal of Computer Applications
%@ 0975-8887
%V 143
%N 7
%P 29-33
%D 2016
%I Foundation of Computer Science (FCS), NY, USA
Abstract

This paper presents minimization technique for multiple value function using Quine Mc-cluskey’s method. This paper provide steps for the minimization of multivalued function i.e. radix >2 digital system. The ternary digital system which radix=3 is considered here minimized function of MVL function implemented using decoder and multiplexer and answer is verified using ternary k-map. As the radix of system increases, the difficulties in the minimization or reduction of logic function is get increases. It becomes difficult to for higher radix to reduce the function design equation. In this paper we successfully applied Quine Mc-Cluskey’s technique to ternary system. In this paper simplified expression designed using decoder and ternary gate. Same expression implemented using ternary multiplexer. Hardware required for both cases is evaluated. It incorporates all designed rules for ternary logic system design and gives the output in the form of Sum-of-Product (SOP) terms.

References
  1. Porat DI. Three-valued Digital Systems. Proc. IEE. 1969; 116: 947-954.
  2. Marek Perkowski (2006): Introduction to multivalued logic Available as: http://web.cecs.pdx.edu/~mperkows temp/JULY/2006.Introduction-to-MV-logic.ppt
  3. S.L.Hurst. (1984): Multivalued logic - Its status and its future, IEEE Trans .on Computers, vol. C-33, pp. 1160-1179..
  4. E. Sipos. et. al. (2008): A Method to Design Ternary Multiplexers Controlled by Ternary Signals Based on SUS-LOC,Proceedings of the IEEE International Conference on Automation, quality and Testing, Robotics, IEEE Computer Society, Vol.3,pp.402-407..
  5. Sheng Lin et al. (2009): CNTFET-Based Design of Ternary Logic Gates and Arithmetic Circuits, IEEE Trans. On Nanotechnology, Vol. PP, Issue.99, pp.1-1.
  6. K. C. Smith. (1981): The Prospects for Multivalued Logic: A Technology and Applications View, IEEE Transactions on Computers, Vol. C-30, Issue.9, pp.619-634...
  7. S.L.Hurst. (1984): Multivalued logic - Its status and its future, IEEE Trans .on Computers, vol. C-33, pp. 1160-1179.
  8. A.P. Dhande (2005): Design And Implementation Of 2 Bit Ternary ALU Slice, 3rd International Conference, Sciences of Electronic (SETIT), IEEE Transc., pp.1-11.
  9. Jorge Pedraza Arpasi (2003): A Brief Introduction to Ternary Logic, pp.1-13.
  10. Raymond E.Miller. (1966): Switching Theory, Vol. I, John Wiley & Sons, pp.8-9
  11. D. I. Porat. (1969): Three-valued digital systems, PROC. IEEE, Vol. 116, No. 6, pp.947-954.
  12. D. Venkat Reddy et. al (2008): Sequential Circuits In The Framework Of (2n+1)-ary Discrete Logic, IJCSNS International Journal of Computer Science and Network Security, Vol.8 No.7, July, pp.175-181..
  13. Jorge Pedraza Arpasi (2003): A Brief Introduction to Ternary Logic, pp.1-13.
  14. Chung-Yu-Wu. Design& application of pipelined dynamic CMOS ternary logic & simple ternary dfferential logic”IEEE journal on solid state circuits. 1993; 28: 895-906.
  15. K.C. Smith. (1988): Multiple-Valued Logic, A Tutorial and Appreciation, Survey & Tutorial Series, IEEE Transc. In computers,Vol.21, Issue.4, pp.17-27
  16. Robert L.Herrmann. (1968): Selection and implementation of a ternary switching algebra, Proceedings of AFIPS Joint Computer Conference, Spring Joint Computer Conference, pp.283-290.
  17. P s wankhade,Dr Gajanan sarate “Optimization of ternary combinational system” IJSER,vol 6,issue5,may2015.
  18. H.T.Moufftah, “Study on Implementation of Three Valued Logic”, Proc.ISMVL, pp.359-372, May 1995.
  19. T.N. Rajashekhara, I-Shi Eric Chen, “Fast Adder Design Using Redundant Sign Digit Number”, International Journal of Electronics, 1990
Index Terms

Computer Science
Information Sciences

Keywords

Multivalued Radix Sum-of-Product (SOP) Ternary Unary function

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