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Optimized CMOS Design of Full Adder using 45nm Technology

by Sheenu Rana, Rajesh Mehra
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International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 142 - Number 13
Year of Publication: 2016
Authors: Sheenu Rana, Rajesh Mehra
10.5120/ijca2016909978

Sheenu Rana, Rajesh Mehra . Optimized CMOS Design of Full Adder using 45nm Technology. International Journal of Computer Applications. 142, 13 ( May 2016), 21-24. DOI=10.5120/ijca2016909978

@article{ 10.5120/ijca2016909978,
author = { Sheenu Rana, Rajesh Mehra },
title = { Optimized CMOS Design of Full Adder using 45nm Technology },
journal = { International Journal of Computer Applications },
issue_date = { May 2016 },
volume = { 142 },
number = { 13 },
month = { May },
year = { 2016 },
issn = { 0975-8887 },
pages = { 21-24 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume142/number13/24958-2016909978/ },
doi = { 10.5120/ijca2016909978 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-06T23:44:59.484503+05:30
%A Sheenu Rana
%A Rajesh Mehra
%T Optimized CMOS Design of Full Adder using 45nm Technology
%J International Journal of Computer Applications
%@ 0975-8887
%V 142
%N 13
%P 21-24
%D 2016
%I Foundation of Computer Science (FCS), NY, USA
Abstract

This paper presents low power full adder designed with pass transistor logic which reduces the area , power and delay. we compared conventional 28T CMOS full adder with 16T and 8T full adder in terms of area , power and delay using 45um Technology The schematic of all three design has been developed and its layout has been created using micro-wind tool. The result show that 8T full adder consumes 98% less power as conventional 28T& 65% less power compared to 16T full adder.

References
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Index Terms

Computer Science
Information Sciences

Keywords

Full adder Pass Transistor logic(PTL) Transmission gate (TG) CMOS Drive current Channel Length.

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