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Optimized CMOS Design of Full Adder using 45nm Technology
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 142 - Number 13 |
| Year of Publication: 2016 |
| Authors: Sheenu Rana, Rajesh Mehra |
10.5120/ijca2016909978
|
Sheenu Rana, Rajesh Mehra . Optimized CMOS Design of Full Adder using 45nm Technology. International Journal of Computer Applications. 142, 13 ( May 2016), 21-24. DOI=10.5120/ijca2016909978
Abstract
This paper presents low power full adder designed with pass transistor logic which reduces the area , power and delay. we compared conventional 28T CMOS full adder with 16T and 8T full adder in terms of area , power and delay using 45um Technology The schematic of all three design has been developed and its layout has been created using micro-wind tool. The result show that 8T full adder consumes 98% less power as conventional 28T& 65% less power compared to 16T full adder.
References
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