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Delay Analysis of Half Subtractor using CMOS and Pass Transistor Logic
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 141 - Number 12 |
| Year of Publication: 2016 |
| Authors: Ishika Sharma, Rajesh Mehra |
10.5120/ijca2016909925
|
Ishika Sharma, Rajesh Mehra . Delay Analysis of Half Subtractor using CMOS and Pass Transistor Logic. International Journal of Computer Applications. 141, 12 ( May 2016), 18-22. DOI=10.5120/ijca2016909925
Abstract
In present day skill, designing of low power systems has emerged as one of the vital theme of electronic industries due to the point that, power consumption is drawing much of the absorption in any very large scale integration (VLSI) chip design. Design of low power circuit for high performance is the necessary main concern of VLSI technique. This paper presents designing of Half Subtractor using basic gates which are drawn by conventional CMOS and Pass Transistor Logics based on 45nm technology . In comparison between the conventional CMOS half subtractor and using Pass Transistor Logic the delay is 10.5% less in PTL’s half subtractor which is due to less number of transistors used in Pass Transistor Logic which in further has reduced the transistor count to 28.57%.
References
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