We apologize for a recent technical issue with our email system, which temporarily affected account activations. Accounts have now been activated. Authors may proceed with paper submissions. PhDFocusTM
CFP last date
20 December 2024
Reseach Article

High Speed Architecture for KECCACK Secure Hash Function

by Pasupuleti Sailaja, Mahendra Vucha
International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 139 - Number 9
Year of Publication: 2016
Authors: Pasupuleti Sailaja, Mahendra Vucha
10.5120/ijca2016909237

Pasupuleti Sailaja, Mahendra Vucha . High Speed Architecture for KECCACK Secure Hash Function. International Journal of Computer Applications. 139, 9 ( April 2016), 19-24. DOI=10.5120/ijca2016909237

@article{ 10.5120/ijca2016909237,
author = { Pasupuleti Sailaja, Mahendra Vucha },
title = { High Speed Architecture for KECCACK Secure Hash Function },
journal = { International Journal of Computer Applications },
issue_date = { April 2016 },
volume = { 139 },
number = { 9 },
month = { April },
year = { 2016 },
issn = { 0975-8887 },
pages = { 19-24 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume139/number9/24518-2016909237/ },
doi = { 10.5120/ijca2016909237 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-06T23:40:29.115769+05:30
%A Pasupuleti Sailaja
%A Mahendra Vucha
%T High Speed Architecture for KECCACK Secure Hash Function
%J International Journal of Computer Applications
%@ 0975-8887
%V 139
%N 9
%P 19-24
%D 2016
%I Foundation of Computer Science (FCS), NY, USA
Abstract

Cryptography is a technique that protects the information, which is in transit or in storage, from unauthorized or unexpected reveals. This paper demonstrates a Secure Hash Algorithm-3(SHA-3) called Keccack, and also proposeda hardware architecture for the Keccack to support high speed security application. Since SHA-3 supports high level of parallelism, the proposed hardware architecture brings higher speed, in terms of bit rate and capacity, and also provides better security demanded by Internet of Things. This paper also demonstrates the architectural attributes of popular and real life cryptography techniques such as, Secure Hash Algorithm-1 (SHA-1), Secure Hash Algorithm-2 (SHA-2) and Advanced Encryption Standard (AES). In this research, the security techniques AES, SHA-1, SHA-2 and SHA-3 has been implemented on Virtex-5 FPGA device and their architectural attributes were captured. Finally, the proposed architecture of SHA-3 is compared with architecture of ontemporary security techniques(AES, SHA-1, and SHA-2) in terms of speed, area and power. The comparison results shown that the SHA-3 architecture brought optimum performance over its contemporary security techniques.

References
  1. Deepthi Barbara Nickolas and Mr. A. Sivasanka,”Design of FPGA Based Encryption Algorithm using KECCAK Hashing Functions”,International Journal of Engineering Trends and Technology (IJETT) - Volume4 Issue6- June 2013
  2. S. Goldwasser, S. Micali and R. Rivest,” A Digital Signature Scheme Secure against Adaptive Chosen-Message Attacks”, SIAM Journal of Computing, vol 17, No. 2, pp. 281-308, April 1998.
  3. S. Haber and W. S. Stornetta. “How to timestampting a digital document”. Journal of Cryptology 3(2), pp. 99-111, 1991.
  4. H. Krawczyk, M. Bellare and R. Canetti. “HMAC: Keyed- Hashing for Message Authentication”. Internet RFC 2104, February 1997.
  5. V. Shoup. “Design and analysis of practical public-key encryption schemes secure against adaptive chosenCipher text attack”. SIAM Journal of Computing 33:167-226, 2003.
  6. Marc Stevens hash clash, “Framework for MD5 & SHA-1 Differential Path Construction and Chosen-Prefix Collisions for MD5”.
  7. X. Wang, H. Yu and Y.L. Yin, “Efficient Collision Search Attacks on SHA-0”, (Pub 2005)
  8. Xiaoyun Wang, X.L., Feng, D., Yu, H.: “Collisions for hash functions MD4, MD5, HAVAL-128 and RIPEMD”. Cryptology ePrint Archive, Report 2004/199, pp. 1–4 (2004), http: // eprint.iacr.org/2004/ 199
  9. Szydlo, M.: “SHA-1 collisions can be found in 263 operations”. Crypto Bytes Technical Newsletter (2005).
  10. ChristofPaar, Jan Pelzl, "Introduction to Public-Key Cryptography", Chapter 6 of "Understanding Cryptography, A Textbook for Students and Practitioners". (companion web site contains online cryptography course that covers public-key cryptography), Springer, 2009.
  11. “Federal Register” / Vol. 72, No. 212 / Friday, November 2 (2007), Notices, http://csrc.nist.gov/groups/ST/hash/documents/FR_Notice_ Nov07.pdf
  12. National Institute of Standards and Technology (NIST).SHA-3 Winner announcement, http: // w ww. nis.gov /itl / csd / sha-100212.cfm.
  13. Walter Tuchman "A brief history of the data encryption standard". Internet besieged: countering cyberspace scofflaws. ACM Press/Addison-Wesley Publishing Co. New York, NY, USA. pp. 275–280.
  14. J.-P. Aumasson, L. Henzen, W. Meier and R. C.-W. Phan, “SHA-3 Proposal BLAKE,” NIST (Round 3), University of California Santa Barbara, Santa Barbara, 2010.
  15. X. Guo, M. Srivastav, S. Huang, D. Ganta, M. B. Henry, L. Nazhandali and P. Schaumont, “Silicon Implementa-tion of SHA-3 Finalists: BLAKE, Grøstl, JH, Keccak and Skein,” Center for Embedded Systems for Critical Appli-cations (CESCA) Bradley Department of Electrical and Computer Engineering Virginia Tech, Blacksburg, 2010.
  16. Mahendra Vucha and Lincy Sara Varghese, “Design Space Exploration of DSP Techniques for Hardware Software Co-Design: An OFDM Transmitter Case Study,” International Journal of Computer Applications, Volume 116, Number 20, pp.29-33, April 2015.
  17. Sudeep M.C, Sharath Bimba M and Mahendra Vucha, “Design and FPGA Implementation of High Speed Vedic Multiplier,” International Journal of Computer Applications, Volume 116, Number 20, pp. 6-9, April 2014.
  18. Mahendra Vucha and ArvindRajawat, “Design and VLSI Implementation of Systolic Array Architecture for Matrix Multiplications,” International Journal of Computer Applications, Volume 26, Number 3, pp. 18-22, April 2011.
  19. Gurjar P., Solanki R., Kansliwal P, Vucha M., "VLSI implementation of adders for high speed ALU," 2011 Annual IEEE in India Conference (INDICON), , vol., no., pp.1-6, 16-18 Dec. 2011.
  20. AUTHORS PROFILE
  21. Pasupuleti Sailaja received her MSc(Tech) in VLSI fromAndhra University in 2013. She is currently pursuing herM.Tech (Communication Systems) in Christ University,Bangalore. Her area of interests are VLSI and Cryptography.
  22. Mahendra Vucha received his B. Tech in Electronics & Communication Engineering from JNTU, Hyderabad in 2007 and M. Tech degree in VLSI and Embedded System Design from MANIT, Bhopal in 2009. He also received Ph. D degree in Electronic and Communication Engineering from MANIT, Bhopal (M.P), India. He is currently working as Asst. Prof in Department of Electronic and Communication Engineering at Faculty of Engineering, Christ University, Bangalore.His areas of interest are Hardware Software Co-
Index Terms

Computer Science
Information Sciences

Keywords

Internet of Things Secure Hash Algorithm Filed Programmable Gate Array.