CFP last date
20 January 2025
Call for Paper
February Edition
IJCA solicits high quality original research papers for the upcoming February edition of the journal. The last date of research paper submission is 20 January 2025

Submit your paper
Know more
The week's pick
Responsive image
SFLA-Based Line Balancing and Task Optimization in Master-Slave Controlled Hanger Transportation Systems for Garment Production

Duc Hoang Nguyen
Random Articles
Reseach Article

Design and Simulation of OTA using DTMOS Technique in 180 nm CMOS Process

by Ali Yazdani-Nejad, S. Hossein Pishgar
journal cover thumbnail

International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 139 - Number 7
Year of Publication: 2016
Authors: Ali Yazdani-Nejad, S. Hossein Pishgar
10.5120/ijca2016909190

Ali Yazdani-Nejad, S. Hossein Pishgar . Design and Simulation of OTA using DTMOS Technique in 180 nm CMOS Process. International Journal of Computer Applications. 139, 7 ( April 2016), 20-22. DOI=10.5120/ijca2016909190

@article{ 10.5120/ijca2016909190,
author = { Ali Yazdani-Nejad, S. Hossein Pishgar },
title = { Design and Simulation of OTA using DTMOS Technique in 180 nm CMOS Process },
journal = { International Journal of Computer Applications },
issue_date = { April 2016 },
volume = { 139 },
number = { 7 },
month = { April },
year = { 2016 },
issn = { 0975-8887 },
pages = { 20-22 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume139/number7/24503-2016909190/ },
doi = { 10.5120/ijca2016909190 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-06T23:40:19.754707+05:30
%A Ali Yazdani-Nejad
%A S. Hossein Pishgar
%T Design and Simulation of OTA using DTMOS Technique in 180 nm CMOS Process
%J International Journal of Computer Applications
%@ 0975-8887
%V 139
%N 7
%P 20-22
%D 2016
%I Foundation of Computer Science (FCS), NY, USA
Abstract

In this paper, a low voltage low power CMOS Operational transconductance amplifier using DTMOS technique is described. The OTA is designed and simulated with 0.18µm CMOS technology. Simulation results show that with DTMOS technique, the open loop gain is 23.05 dB, the unity gain bandwidth is 379.7 KHz, phase margin is 93.8 degree, power consumption is 1.397 µw and input noise is 25.71 nv2/Hz at 1 Hz frequency while operating at 0.6 v supply voltage and under 1 pF capacitor load. DTMOS technique provide low noise compared to conventional OTA. So DTMOS technique is suitable for low noise and low power applications such as biomedical applications.

References
  1. D. Liu and C. Svensson, “Trading speed for low-power by choice of supply and threshold voltages,” IEEE J. Solid-State Circuits, vol. 28, pp. 10–17, Jan. 1993.
  2. F. Assaderaghi, D. Sinitsky, S. Parke, J. Bokor, P. K. Ko, and C. Hu, “A dynamic threshold voltage MOSFET (DTMOS) for ultra-low voltage operation,” in Int. Electron Devices Meeting, Techn. Digest, 1994, pp. 809–812.
  3. F. Assaderaghi, D. Sinitsky, S. Parke, J. Bokor, P.K. Ko and Hu. Chenming, “Dynamic Threshold-Voltage MOSFET (DTMOS) for Ultra-Low Voltage VLSI,” IEDM Trans, vol. 44 Mar 1997, pp. 414-422.
  4. S. Voldman, D. Hui, D. Young, R. Williams, D. Dreps, J. Howard, M. Sherony, F. Assaderaghi and G. Shahidi, “Silicon-on-insulator dynamic threshold ESD networks and active clamp circuitry” in Proc. Electrical Overstress/Electrostatic Discharge Symposium, 2000, pp. 29-40.Sannella, M. J. 1994 Constraint Satisfaction and Debugging for Interactive User Interfaces. Doctoral Thesis. UMI Order Number: UMI Order No. GAX95-09398., University of Washington.
  5. Baker, R.J, CMOS: Circuit Design, Layout, and Simulation,2008,wiley
  6. B. Razavi, Design of Analog CMOS Integrated Circuits. New York, NY: McGraw-Hill, 2001
  7. Twinkle Patel, Kishen Raikar, Sharan Hiremath, Prof. Sneha Meti, “Design of Balanced Operational Transconductance Amplifier (OTA)” International Journal of Emerging Technology in Computer Science & Electronics (IJETCSE) ISSN: 0976-1353 Volume 14 Issue 2 –APRIL 2015
  8. E. Kargaran, M. Sawan, Kh. Mafinezhad and H. Nabovati, “Design of 0.4V, 386nW OTA Using DTMOS Technique for Biomedical Applications” in Proc. 55th IEEE International Midwest Symposium on Circuits and Systems, 2012, pp. 270–273
  9. H.F. Achigui, C.J.B. Fayomi and M. Sawan “A 1V Low-Power Low-Noise DTMOS Based Class AB Op amp,” Proc. IEEE NEWCAS, pp. 307–310, 2005
  10. G. Raikos and S. Vlassis, “0.8 V bulk-driven operational amplifier,” Analog Integr Circ Sig Process (2010) 63:425–432.
Index Terms

Computer Science
Information Sciences

Keywords

DTMOS OTA open loop gain unity gain bandwidth phase margin.

Powered by PhDFocusTM