CFP last date
20 January 2025
Call for Paper
February Edition
IJCA solicits high quality original research papers for the upcoming February edition of the journal. The last date of research paper submission is 20 January 2025

Submit your paper
Know more
The week's pick
Responsive image
SFLA-Based Line Balancing and Task Optimization in Master-Slave Controlled Hanger Transportation Systems for Garment Production

Duc Hoang Nguyen
Random Articles
Reseach Article

Effects of High-k Dielectric Materials on Electrical Characteristics of DG n-FinFETs

by Nour El Islam Boukortt, Baghdad Hadri, Salvatore Patanè
journal cover thumbnail

International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 139 - Number 10
Year of Publication: 2016
Authors: Nour El Islam Boukortt, Baghdad Hadri, Salvatore Patanè
10.5120/ijca2016909385

Nour El Islam Boukortt, Baghdad Hadri, Salvatore Patanè . Effects of High-k Dielectric Materials on Electrical Characteristics of DG n-FinFETs. International Journal of Computer Applications. 139, 10 ( April 2016), 28-32. DOI=10.5120/ijca2016909385

@article{ 10.5120/ijca2016909385,
author = { Nour El Islam Boukortt, Baghdad Hadri, Salvatore Patanè },
title = { Effects of High-k Dielectric Materials on Electrical Characteristics of DG n-FinFETs },
journal = { International Journal of Computer Applications },
issue_date = { April 2016 },
volume = { 139 },
number = { 10 },
month = { April },
year = { 2016 },
issn = { 0975-8887 },
pages = { 28-32 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume139/number10/24528-2016909385/ },
doi = { 10.5120/ijca2016909385 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-06T23:40:35.552636+05:30
%A Nour El Islam Boukortt
%A Baghdad Hadri
%A Salvatore Patanè
%T Effects of High-k Dielectric Materials on Electrical Characteristics of DG n-FinFETs
%J International Journal of Computer Applications
%@ 0975-8887
%V 139
%N 10
%P 28-32
%D 2016
%I Foundation of Computer Science (FCS), NY, USA
Abstract

This paper investigates the electrical characteristics of the nanoscale n-channel double gate fin field-effect transistor (FinFET) structures and their sensitivity to gate dielectric materials with different channel materials using SiGe and 3C-SiC in the channel region. In this work, the numerical tool Atlas Silvaco was used to simulate the device in three dimensions and evaluate the electrical characteristics of the device at 300K. The influence of the gate dielectrics on threshold voltage roll-off, subthreshold slope, transconductance, drain induced barrier lowering, leakage current, on-current, and on/off current ratio has been investigated. The simulation results show that high drain current and transconductance were obtained with SiGe channel material. The results also show that a higher value of gate dielectric constant can increase the drain current and improve the leakage current. Drain induced barrier lowering is reduced with the increase in gate dielectric constant. It can be noticed with different and useful results which led researchers to further manufacturing process in order to get the complete device.

References
  1. J-P. Colinge, 2008 FinFETs and Other Multi-Gate Transistors, New York: Springer US, p 355.
  2. Narendar, V. and Mishra, R. A. 2015 Analytical modeling and simulation of multigate FinFET devices and the impact of high-k dielectrics on short channel effects (SCEs), Superlattices Microstruct., 85, 357-369.
  3. D. Hisamoto, et al, 2000 FinFET—A Self-Aligned Double-Gate MOSFET Scalable to 20 nm, IEEE Trans. Electron Devices, vol. 47, 2320-2325.
  4. N. Boukortt, et al., 2015 3-D Simulation of Nanoscale SOI n-FinFET at a Gate Length of 8 nm Using ATLAS SILVACO, Trans. Electr. Electron. Mater. vol. 16, 2-7.
  5. N. Boukortt, B. Hadri, and A. Caddemi, 2016 Simulation of a Nanoscale SOI TG nFinFET, Int J Comput Appl., Vol. 138, 10-14.
  6. C. R. Selvakumar, et al, 1991 SiGe-Channel n-MOSFET by Germanium Implantation, IEEE Electron Device Lett,. vol. 12, 444-446.
  7. G. S. Chung, et al, 2010 Electrical characterization of Au/3C-SiC/n-Si/Al Schottky junction J. Alloys Compd. vol. 507, 508-512.
  8. R. P. Ortiz, et al, 2010 High-k Organic, Inorganic, and Hybrid Dielectrics for Low-Voltage Organic Field-Effect Transistors, Chem. Rev. vol. 110, 205-239.
  9. S. International, 2012 Atlas User's Manual Device Simulation Software (Silvaco Int., Santa Clara).
  10. C. Meinhard, et al, 2014 Predictive evaluation of electrical characteristics of sub-22 nm FinFET technologies under device geometry variations, Microelectron. Reliab. vol. 54, 2319-2324.
  11. G. Hu, et al. 2016 Analytical models for channel potential, threshold voltage, and subthreshold swing of junctionless triple-gate FinFETs, Microelectr J. vol. 50, 60–65.
  12. S. K. Mohapatra, et al, 2013 Some Device Design Considerations to Enhance the Performance of DG-MOSFETs, Trans. Electr. Electron. Mater. vol. 14, 291-294.
  13. K. P. Pradhan et al. 2016 Exploration of symmetric high-k spacer (SHS) hybrid FinFET for high performance application. Superlattices Microstruct., 90, 191-197.
  14. W. T. Huang, and Y. Li. 2015 Electrical characteristic fluctuation of 16-nm-gate trapezoidal bulk FinFET devices with fixed top-fin width induced by random discrete dopants. Nanoscale Res Lett., 10:116:1-8.
  15. K. P. Pradhan, Priyanka, and P.K. Sahu 2016 Temperature dependency of double material gate oxide (DMGO) symmetric dual-k spacer (SDS) wavy FinFET. Superlattice Microst., 89, 355-361.
Index Terms

Computer Science
Information Sciences

Keywords

Nanoscale Double gate FinFEts SCEs DIBL Silvaco Software.

Powered by PhDFocusTM