The week's pick
Random Articles
Reseach Article
18 Years of Redundant Basis Multipliers over Galois Field
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 138 - Number 13 |
| Year of Publication: 2016 |
| Authors: Roma Chourasia, Kavita Khare |
10.5120/ijca2016908878
|
Roma Chourasia, Kavita Khare . 18 Years of Redundant Basis Multipliers over Galois Field. International Journal of Computer Applications. 138, 13 ( March 2016), 1-5. DOI=10.5120/ijca2016908878
Abstract
Redundant basis multipliers over Galois Field have gained huge popularity in elliptic curve cryptography mainly because of their negligible hardware cost for squaring and modular reduction. Different techniques used so far for the implementation of redundant basis multipliers over Galois Field are explored here. Based on review the Word Level Redundant Basis multiplier is the most efficient among all multipliers in terms of hardware utilization. Digit serial Redundant Basis multiplication in a bit level matrix vector form is most efficient in terms of area-time complexities.
References
- Alessandro Cilardo, Luigi Coppolino, Nicola Mazzocca, and Luigi Romano, “Elliptic Curve Cryptography Engineering,” proc. of IEEE, vol.94, no.2, pp.395-406, Feb.2006.
- N.R.Murthy and M.N.S.Swamy, “Cryptographic applications of brahmagupta-bhaskara equation,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol.53, no.7, pp.1565-1571, 2006.
- L.Song and K.K.Parhi, “Low-energy digit-serial/parallel finite field multipliers,” J.VLSI Digit. Process, vol.19, pp.149-166, 1998.
- P.K.Meher, “On efficient implementation of accumulation in finite field over GF (2^m) and its applications,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol.17, no.4, pp.541-550, 2009.
- L.Song, K.K.Parhi, I.Kuroda, and T.Nishitani, “Hardware / software codesign of finite field data path for low-energy Reed-Solomn codecs,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol.8, no.2, pp.160-172, Apr.2000.
- G.Drolet, “A new representation of elements of finite fields GF (2^m) yielding small complexity arithmetic circuits,” IEEE Trans. Comput., vol.47, no.9, pp.938-946, 1998.
- C.Y.Lee, J.S.Horng, I.C.Jou, and E.H.Lu, “Low-complexity bit parallel systolic Montgomery multipliers for special classes of GF (2^m),” IEEE Trans. Comput., vol.54, no.9, pp.1061-1070, Sep.2005.
- P.K.Meher, “Systolic and super-systolic multipliers for finite field GF (2^m) based on irreducible trinomials,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol.55, no.4, pp.1031-1040, May 2008.
- J.Xie, J.He, and P.K.Meher, “Low latency systolic Montgomery multiplier for finite field GF (2^m) based on pentanomials,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol.21, no.2, pp.385-389, Feb.2013.
- H.Wu, M.A.Hasan, I.F.Blake, and S.Gao, “Finite field multiplier using redundant representation,” IEEE Trans. Comut., vol.51, no.11, pp.1306-1316, Nov.2002.
- A.H.Namin, H.Wu, and M.Ahmadi, “Comb architectures for finite field multiplication in F2m,” IEEE Trans. Comput., vol.56, no.7, pp.909-916, Jul.2007.
- A.H.Namin, H.Wu, and M.Ahmadi, “A new finite field multiplier using redundant representation,” IEEE Trans. Comput., vol.57, no.5, pp.716-720, May 2008.
- A.H.Namin, H.Wu, and M.Ahmadi, “A high-speed word level ?nite ?eld multiplier F2m in using redundant representation,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 17, no.10, pp.1546-1550, Oct.2009.
- A. H. Namin, H. Wu, and M. Ahmadi, “An ef?cient ?nite ?eld multiplier using redundant representation,” ACM Trans. Embedded Comput. Sys., vol. 11, no. 2, Jul. 2012, Art. 31.
- G.Yuvaraj, Anusree.G, Manopriya.K, Shobana.T, Yasodha.R Final, “Design of Word Level Multiplication Algorithm on reordered normal Basis,” International Journal of Innovations in Engineering and Technology (IJIET),vol.1, Issue 4, pg.88-94, December 2012.
- Jiafeng Xie, P.K.Meher, Zhi-Hong Mao, “High Throughput Finite Field Multipliers Using Redundant Basis for FPGA and ASIC Implementations,” IEEE Trans. Circuits and Systems, vol.62, no.1, pp.110-119, January 2015.
- W.Geiselmann, J.Muller-Quade, and R.Steinwandt, "On "A New Representation of Elements of Finite Fields GF (2^m) Yielding Small Complexity Arithmetic Circuits,” IEEE Trans. Computers, vol. 51, no. 12, pp. 1460-1461, Dec. 2002.
- W.Geiselmann and H.Lukhaub, "Redundant Representation of Finite Fields," Proc. Public Key Cryptography, pp. 339-352, 2001.
- R.Katti and J.Brennan, "Low Complexity Multiplication in a Finite Field Using Ring Representation," IEEE Trans. Computers, vol. 52, no. 4, pp. 418-426, April 2003.
Index Terms
Keywords