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Current Comparison based Domino with Clamped Bit-Line Current Amplifier for Wide Fan-In Gates
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 137 - Number 5 |
| Year of Publication: 2016 |
| Authors: K. Sangeetha, V. Venmathi, P. Ramya, B. Kalaimathi |
10.5120/ijca2016907944
|
K. Sangeetha, V. Venmathi, P. Ramya, B. Kalaimathi . Current Comparison based Domino with Clamped Bit-Line Current Amplifier for Wide Fan-In Gates. International Journal of Computer Applications. 137, 5 ( March 2016), 1-3. DOI=10.5120/ijca2016907944
Abstract
A greater part of the low power design methodology is allocated for reducing leakage current. This plays a vital role in static power dissipation. In this project, a current comparison domino pull-up network with its worst case leakage current is compared with Current comparison based Domino (CCD) with Clamped bit-line Current-sensing Amplifier circuit. Thus, the contention current and consequently power consumption and delay are reduced. The leakage current is also decreased by utilizing the footer transistor in diode configuration, which results in increased noise immunity. The simulation results of wide fan-in gates designed using a 16-nm high-performance predictive technology model demonstrates 46 % power reduction and at least 2.36× noise-immunity improvement at the same delay compared to the standard domino circuits for wide fan – in OR gates.
References
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