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Optimized High Performance 10T SRAM Cell Characterization

by Arjun Singh Yadav, Sangeeta Nakhte
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International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 134 - Number 5
Year of Publication: 2016
Authors: Arjun Singh Yadav, Sangeeta Nakhte
10.5120/ijca2016907964

Arjun Singh Yadav, Sangeeta Nakhte . Optimized High Performance 10T SRAM Cell Characterization. International Journal of Computer Applications. 134, 5 ( January 2016), 29-33. DOI=10.5120/ijca2016907964

@article{ 10.5120/ijca2016907964,
author = { Arjun Singh Yadav, Sangeeta Nakhte },
title = { Optimized High Performance 10T SRAM Cell Characterization },
journal = { International Journal of Computer Applications },
issue_date = { January 2016 },
volume = { 134 },
number = { 5 },
month = { January },
year = { 2016 },
issn = { 0975-8887 },
pages = { 29-33 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume134/number5/23912-2016907964/ },
doi = { 10.5120/ijca2016907964 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-06T23:33:22.233901+05:30
%A Arjun Singh Yadav
%A Sangeeta Nakhte
%T Optimized High Performance 10T SRAM Cell Characterization
%J International Journal of Computer Applications
%@ 0975-8887
%V 134
%N 5
%P 29-33
%D 2016
%I Foundation of Computer Science (FCS), NY, USA
Abstract

In this work, optimized Low power and high speed SRAM architecture based on ten transistor (10T) bit-cell is proposed. This cell obtains low static power and high speed read due to two independent read access mechanisms, which offers cascading of read driver. It also estimates read/write delay, read stability, write stability and compare the result with that of standard 6T, 9T and LP10T SRAM cell. The comparative study based on VDD and Temperature variation using simulation exhibits appreciable improvement in read delay and write SNM.

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Index Terms

Computer Science
Information Sciences

Keywords

Standby Powers Read Operation Delay Write Operation Delay Monte Carlo Simulation and Static Noise Margin.

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