We apologize for a recent technical issue with our email system, which temporarily affected account activations. Accounts have now been activated. Authors may proceed with paper submissions. PhDFocusTM
CFP last date
20 December 2024
Call for Paper
January Edition
IJCA solicits high quality original research papers for the upcoming January edition of the journal. The last date of research paper submission is 20 December 2024

Submit your paper
Know more
The week's pick
Responsive image
Improved Shuffled Frog Leaping Algorithm with Self-Adaptive Shuffling for Fuzzy Logic PD+G Controller Optimization in Robotic Manipulators

Duc Hoang Nguyen
Random Articles
Reseach Article

Optimized High Performance 10T SRAM Cell Characterization

by Arjun Singh Yadav, Sangeeta Nakhte
journal cover thumbnail

International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 134 - Number 5
Year of Publication: 2016
Authors: Arjun Singh Yadav, Sangeeta Nakhte
10.5120/ijca2016907964

Arjun Singh Yadav, Sangeeta Nakhte . Optimized High Performance 10T SRAM Cell Characterization. International Journal of Computer Applications. 134, 5 ( January 2016), 29-33. DOI=10.5120/ijca2016907964

@article{ 10.5120/ijca2016907964,
author = { Arjun Singh Yadav, Sangeeta Nakhte },
title = { Optimized High Performance 10T SRAM Cell Characterization },
journal = { International Journal of Computer Applications },
issue_date = { January 2016 },
volume = { 134 },
number = { 5 },
month = { January },
year = { 2016 },
issn = { 0975-8887 },
pages = { 29-33 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume134/number5/23912-2016907964/ },
doi = { 10.5120/ijca2016907964 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-06T23:33:22.233901+05:30
%A Arjun Singh Yadav
%A Sangeeta Nakhte
%T Optimized High Performance 10T SRAM Cell Characterization
%J International Journal of Computer Applications
%@ 0975-8887
%V 134
%N 5
%P 29-33
%D 2016
%I Foundation of Computer Science (FCS), NY, USA
Abstract

In this work, optimized Low power and high speed SRAM architecture based on ten transistor (10T) bit-cell is proposed. This cell obtains low static power and high speed read due to two independent read access mechanisms, which offers cascading of read driver. It also estimates read/write delay, read stability, write stability and compare the result with that of standard 6T, 9T and LP10T SRAM cell. The comparative study based on VDD and Temperature variation using simulation exhibits appreciable improvement in read delay and write SNM.

References
  1. Pavlov A, Sachdev M. CMOS SRAM circuit design and parametric test in nanoscaled technologies: process-aware SRAM design and test. Springer; 2008.
  2. Maziar G, Tohru I, Hamid N. Variation-aware software techniques for cache leakage reduction using value-dependence of SRAM leakage due to within-die process variation. In: Proceedings of the 3rd international conference on High performance embedded architectures and compilers. Springer-Verlag: Goteborg, Sweden; 2008.
  3. E. Grossar et al., “Read stability and write-ability analysis of SRAM cells for nanometer technologies,” IEEE J. Solid-State Circuits , vol. 41, no. 11, pp. 2577–2588, Nov. 2006.
  4. V. Gupta and M. Anis, “Statistical design of the 6T SRAM bit cell,” IEEETrans.CircuitsSyst.I,Reg.Papers , vol. 57, no. 1, pp. 93–104, Mar. 2010.
  5. J. Singh, D. K. Pradhan, S. Hollis, and S. P. Mohanty, “A single ended 6T SRAM cell design for ultra-low-voltage applications,” IEICE Electron.Exp., vol. 5, no. 18, pp. 750–755, Sep. 2008.
  6. H. Mizuno and T. Nagano, “Driving source-line cell architecture for sub-1-V high-speed low-power applications,” IEEE J. Solid-State Circuits, vol. 31, no. 4, pp. 552–557, Apr. 1996.
  7. Z. Liu and V. Kursun, “Characterization of a novel nine-transistor SRAM cell,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 16, no. 4, pp. 488–492, Apr. 2008.
  8. Islam A, Mohd. Hasan(2012), “Leakage characterization of 10T SRAM cell,” IEEE Transaction Electron Device, 59(3), 631-638.
  9. Verma N, Kong J, Chandrakasan A.P., “Nanometer MOSFET variation in minimum energy subthreshold circuits,” IEEE Transaction Electron Device, vol.55, no.1, pp.163–174, Jan. 2008.
  10. Rabaey Jan M, Chandrakasan Anantha, Nikolic Borivoje, “Digital integrated circuits: a design perspective”, 2nd ed., New Delhi: Prentice-Hall of India; 2005.
  11. Cao Yu, “Nanoscale Integration and Modeling (NIMO) Group, Arizona State University (ASU)”, http://ptm.asu.edu/, 2014.
  12. Islam A, Mohd. Hasan, “Leakage characterization of 10T SRAM cell”, IEEE Trans. Electron Dev., vol. 59, no. 3, pp. 631-638, March 2012.
  13. Guo Z. et al., “Large-scale SRAM variability characterization in 45nm CMOS”, IEEE J. Solid-State Circuit, vol.44, no.11, Nov. 2009, pp. 3174–3192.
  14. Bhavnagarwala A. et al., “A sub-600 mV, fluctuation tolerant 65-nm CMOS SRAM array with dynamic cell biasing”, IEEE J. Solid-State Circuit, vol. 43, no.4, pp.946–955, April 2008.
  15. Islam A, Mohd. Hasan, “A technique to mitigate impsact of process voltage and temperature variations on design metrics of SRAM cell”, Microelectronics Reliability, vol.52, no.2, pp. 405-411, Fab. 2011.
  16. A. E. Carlson, “Device and circuit techniques for reducing variation in nanoscale SRAM,” Ph.D. dissertation, Univ. California Berkeley, Berkeley, CA, May 2008.
  17. Available:http://wwwdevice.eecs.berkeley.edu/~bsim3/bsim4_get.html.
  18. J.-M. Wang, S.-C. Fang, and W.-S. Feng, “New efficient designs for XOR and XNOR functions on the transistor level,” IEEE J. Solid-State Circuits, vol. 29, no. 7, pp. 780–786, Jul. 1994.
  19. J.-F. Lin, Y.-T. Hwang, M.-H. Sheu, and C.-C. Ho, “A novel high-speed and energy efficient 10-transistor full adder design,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 54, no. 5, pp. 1050-1059, May 2007.
Index Terms

Computer Science
Information Sciences

Keywords

Standby Powers Read Operation Delay Write Operation Delay Monte Carlo Simulation and Static Noise Margin.

Powered by PhDFocusTM