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Implementation of Delay Efficient ALU using Vedic Multiplier with AHL
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 133 - Number 6 |
| Year of Publication: 2016 |
| Authors: P. Vimala, Swapna M.S. |
10.5120/ijca2016907862
|
P. Vimala, Swapna M.S. . Implementation of Delay Efficient ALU using Vedic Multiplier with AHL. International Journal of Computer Applications. 133, 6 ( January 2016), 34-40. DOI=10.5120/ijca2016907862
Abstract
Digital multipliers are most widely used component in applications such as convolution, Fourier transform, discrete cosine transforms, and digital filtering. Because outturn of these applications mainly depends on multiplier speed, therefore multipliers must be designed efficiently. In the proposed architecture, a variable-latency multiplier design with novel AHL architecture and a razor flip flop is used, which results in reduced delay and increased speed than the existing system. Meanwhile proposed architecture is used to compare array multiplier, column-bypassing multiplier, row-bypassing multiplier and Vedic multiplier. The experimental result shows that the Vedic multiplier has better performance in power consumption and delay. Here in this work Vedic multiplication is done using Urdhva Tiryakbhyam Sutra (Algorithm), which results in minimum delay. Thus using Vedic multiplier ALU is designed which results in enhanced performance compared to contemporary design.
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