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A BBS Random Number Generator for Low Power Applications
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 131 - Number 3 |
| Year of Publication: 2015 |
| Authors: Alireza Hassanzadeh, Vahid Mahboubi |
10.5120/ijca2015907230
|
Alireza Hassanzadeh, Vahid Mahboubi . A BBS Random Number Generator for Low Power Applications. International Journal of Computer Applications. 131, 3 ( December 2015), 33-36. DOI=10.5120/ijca2015907230
Abstract
In this paper a low power random number generator has been designed and implemented using BBS algorithm. The BBS random number generator is known for high statistical quality and power consumption. Dynamic power dissipation has been reduced significantly comparing to regular implementation. Low power techniques such as power gating and pipelining have been employed to reduce power consumption of the module. Experimental measurements for a 32-bit BBS random number generator shows at least 30% reduction in dynamic power consumption. The proposed low power BBS random number generator has been implemented on Xilinx Spartan-6 FPGA evaluation board.
References
- A. Tomoaki Sato B. Kazuhira Kikuchi C. Masa-aki Fukase, "A PRNG Circuit on PLD with Feature of Low- Power, High-Speed, and Various Generation of Random Number Sequence", Hirosaki, Aomori 036-8561 JAPAN, IEEE 2006.
- A. K.H. Tsoi B. K.H. Leung C. P.H.W. Leong,“Compact FPGA-based True and Pseudo Random Number Generator", Proceedings of the 11th Annual IEEE Symposium on Field-Programmable Custom Computing Machines IEEE 2003.
- A.Khushboo Sewak, B.Praveena Rajput, C. Amit Kumar Panda, ”FPGA Implementation of 16 bit BBS and LFSR PN Sequence Generator: A Comparative Study" 2012 IEEE Students’ Conference on Electrical, Electronics and Computer Science FPGA.
- A.Tomoaki Sato B.Kazuhira Kikuchit C. Masa-aki Fukaset, "Chip Design of a Wave-Pipelined PRNG",2006 IEEE
- Xilinx, Inc. Xilinx Libraries Guide, 2011.
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