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Error Detection in 2-bit & 4-bit Multiplier using Parity Predictor Circuit in QCA
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 131 - Number 15 |
| Year of Publication: 2015 |
| Authors: Ankita Laad, Namit Gupta, Nilesh Patidar |
10.5120/ijca2015907414
|
Ankita Laad, Namit Gupta, Nilesh Patidar . Error Detection in 2-bit & 4-bit Multiplier using Parity Predictor Circuit in QCA. International Journal of Computer Applications. 131, 15 ( December 2015), 27-31. DOI=10.5120/ijca2015907414
Abstract
Error detection is the detection of errors caused by noise or other impairments during the transmission of signal from transmitter to receiver. Logic design errors may occur during simulation and synthesis due to increase in the complexity of CMOS and VLSI circuits. Error detection method can be either systematic or non-systematic. In systematic method, the transmitter sends the original data unit, and a fixed number of check bits or Parity data is been attached to it, which are derived from the same input data unit. In this work, we describe a method of error detection in 4-bit multiplier with parity predictor circuit in QCA tool. 4-bit multiplier is used as a logic in which we detect error according to its input data. The outputs of logic used and the parity predictor are then compared using comparator. If the values do not match, error has occurred. The technique we used is Concurrent error detection using parity predictor circuit.
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