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An Efficient Processing by using Kogge-Stone High Speed Addition Technique
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 131 - Number 1 |
| Year of Publication: 2015 |
| Authors: Rajnish Dubey, Jitendra Jain |
10.5120/ijca2015907211
|
Rajnish Dubey, Jitendra Jain . An Efficient Processing by using Kogge-Stone High Speed Addition Technique. International Journal of Computer Applications. 131, 1 ( December 2015), 21-23. DOI=10.5120/ijca2015907211
Abstract
In this Technical era the high speed and low area of VLSI chip are very- very essential factors. Day by day number of transistors and other active and passive elements are drastically growing on VLSI chip. All the processors of the devices adders and multipliers are played an important role. Adder is a striking element for the designing of fast multiplier. Ultimately here need a fast adder for high bit addition. In this paper, proposed Kogge-Stone adders are used for binary addition to reduce the size and increase the efficiency or processors speed. Proposing Kogge stone adder provides less components, less path delay and better speed compare to other existing Kogge Stone adder and other adders. Here we are comparing the Kogge Stone adders of different-different word size from other adders. The design and experiment can be done by the aid of Xilinx 14.2i Spartan 3E device family.
References
- Soma BhanuTej, 2012.Vedic Algorithms to develop green chips for future, International Journal of Systems, Algorithms and Applications, Volume 2, Issue ICAEM12, ISSN Online: 22772677..
- Youngjoon Kim and Lee-Sup Kim, 2001.A low power carry select adder with reduced area,IEEE International Symposium on Circuits and Systems, vol.4, pp.218-221. Tavel, P. 2007 Modeling and Simulation Design. AK Peters Ltd.
- Akhilesh Tyagi,1990.A Reduced Area Scheme for Carry- Select Adders,IEEE International Conference on Computer design, pp.255-258..
- Belle W.Y.Wei and Clark D.Thompson,1990.Area-Time Optimal Adder Design, IEEE transactions on Computers, vol.39, pp. 666675.
- Y. Choi, 2005.Parallel Prefix Adder Design, Proc. 17th IEEE Symposium on Computer Arithmetic, pp 90-98.
- Kogge P and Stone H, 1973.A Parallel Algorithm for the Efficient Solution of a General Class of Recurrence Relations, IEEE Transactions on Computers, Vol. C-22, No. 8, pp. 786-793.
- Madhu Thakur and Javed Ashraf, 2012.Design of Braun Multiplier with Kogge-Stone Adder and Its Implementation on FPGAInternational Journal of Scientific and Engineering Research, Vol. 3, No. 10, pp. 03-06, ISSN 2229-5518.
- Pakkiraiah Chakali and Madhu Kumar Patnala , 2013.Design of High Speed Kogge-Stone Based Carry Select Adder, International Journal of Emerging Science and Engineering (IJESE), Vol. 1, No. 4, ISSN: 2319-6378.
- Somayeh Babazadeh and Majid Haghparast, 2012.Design of a Nanometric Fault Tolerant Reversible Multiplier Circuit, Journal of Basic and Applied Scientific Research.
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