The week's pick
Reseach Article
Rational Sampling Rate Converter using Coefficient Symmetry
by
Rajesh Mehra,
Vandita Singh
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 129 - Number 4 |
| Year of Publication: 2015 |
| Authors: Rajesh Mehra, Vandita Singh |
10.5120/ijca2015906795
|
Rajesh Mehra, Vandita Singh . Rational Sampling Rate Converter using Coefficient Symmetry. International Journal of Computer Applications. 129, 4 ( November 2015), 1-7. DOI=10.5120/ijca2015906795
@article{
10.5120/ijca2015906795,
author = {
Rajesh Mehra,
Vandita Singh
},
title = { Rational Sampling Rate Converter using Coefficient Symmetry },
journal = {
International Journal of Computer Applications
},
issue_date = { November 2015 },
volume = { 129 },
number = { 4 },
month = { November },
year = { 2015 },
issn = { 0975-8887 },
pages = {
1-7
},
numpages = {9},
url = {
https://ijcaonline.org/archives/volume129/number4/23058-2015906795/
},
doi = { 10.5120/ijca2015906795 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-06T23:22:29.112679+05:30
%A Rajesh Mehra
%A Vandita Singh
%T Rational Sampling Rate Converter using Coefficient Symmetry
%J International Journal of Computer Applications
%@ 0975-8887
%V 129
%N 4
%P 1-7
%D 2015
%I Foundation of Computer Science (FCS), NY, USA
Abstract
In this paper, we proposes an efficient structure for rational sampling rate converter. Finite impulse response filter is used in between upsampler and downsampler in order to avoid image spectra and aliasing effects respectively. Coefficient symmetry of the linear phase filter is used so that number of required multiplication per output sample is reduced.
References
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- rejection,” IEEE Latin America Symposium on Circuits andSystems, pp.1-4, 2012.Robert Bregovic, Tapio Saramaki, Ya Jun Yu, and Yong Ching Lim, “An Efficient Implementation of Linear-Phase FIR Filters for a Rational Sampling Rate Conversion”, IEEE International Conference on circuits and systems, pp. 453- 498, 2006.
- Rajesh Mehra, Swapna Devi, “FPGA Based Design of High Performance Decimator using DALUT Algorithm”, ACEEE International Journal on Signal and Image Processing, Volume 1, pp. 9-13, 2010.
- Rajesh Mehra, and Lajwanti Singh, “cost analysis and simulation of decimator for multirate applications,” International Journal of Computers & Technology, vol. 11, no. 1, pp.2175-2181, 2013
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- Rajesh Mehra and Swapna Devi, “Efficient Hardware Co-Simulation of Down Converter for Wireless Communication Sysrems”, International Journal of VLSI Design and communication Systems, Volume 1, No. 2, pp. ,June 2010.
- Rajesh Mehra and Ravinder kaur, “Reconfigurable Area and Speed Efficient Interpolator using DALUT Algorithm”, Advanced in Networks and Communications, Volume 132, pp.117-125, 2011.
- Rajesh Mehra , “FPGA Design of Optimized CIC Interpolator for DSP Based Wireless Communication System”, IMS MANTHAN Journal of Mgt., Computer Science and Journalism, Volume 5, Issue-2, pp. 43-46, 2010.
- Rajesh Mehra and Swapna Devi “Optimized Design of Decimator for Alias Removal in Multirate DSP applications”, Nonlinear System and Wavelet Analysis, pp. 100-103, 2010
- Robert Bregovic, Ya JunYu, Tapio Saramaki, “ Implementation of Linear-Phase FIR Filters for a Rational Sampling-Rate Conversion Utilizing the Coefficient Symmetry”, IEEE Transactions on circuits and systems, Vol. 58, No. 3, pp. 548-561, MARCH 2011.
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- Yong Ching Lim. "An Efficient Implementation of Linear-Phase FIR Filters for a Rational Sampling Rate Conversion", IEEE International Symposium onCircuits and Systems ISCAS-06, 2006.
Index Terms
Computer Science
Information Sciences
Keywords