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Reseach Article

Rational Sampling Rate Converter using Coefficient Symmetry

by Rajesh Mehra, Vandita Singh
International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 129 - Number 4
Year of Publication: 2015
Authors: Rajesh Mehra, Vandita Singh
10.5120/ijca2015906795

Rajesh Mehra, Vandita Singh . Rational Sampling Rate Converter using Coefficient Symmetry. International Journal of Computer Applications. 129, 4 ( November 2015), 1-7. DOI=10.5120/ijca2015906795

@article{ 10.5120/ijca2015906795,
author = { Rajesh Mehra, Vandita Singh },
title = { Rational Sampling Rate Converter using Coefficient Symmetry },
journal = { International Journal of Computer Applications },
issue_date = { November 2015 },
volume = { 129 },
number = { 4 },
month = { November },
year = { 2015 },
issn = { 0975-8887 },
pages = { 1-7 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume129/number4/23058-2015906795/ },
doi = { 10.5120/ijca2015906795 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-06T23:22:29.112679+05:30
%A Rajesh Mehra
%A Vandita Singh
%T Rational Sampling Rate Converter using Coefficient Symmetry
%J International Journal of Computer Applications
%@ 0975-8887
%V 129
%N 4
%P 1-7
%D 2015
%I Foundation of Computer Science (FCS), NY, USA
Abstract

In this paper, we proposes an efficient structure for rational sampling rate converter. Finite impulse response filter is used in between upsampler and downsampler in order to avoid image spectra and aliasing effects respectively. Coefficient symmetry of the linear phase filter is used so that number of required multiplication per output sample is reduced.

References
  1. Yu Huijun, “Design Of A Sample-Rate Converter Based On Least-Square Method”, IEEE International Conference on computer science and Information processing, pp. 332-335, June 2012.
  2. Robert Bregovic, Ya Jun Yu and Ari Viholainen, “Implementation of Linear-Phase FIR Nearly Perfect Reconstruction Cosine-Modulated Filter banks Utilizing the Coefficient Symmetry”, IEEE Transactions on circuits and systems, Vol. 57, No. 1, pp. 139-151, January 2010.
  3. Oscar Gutafsson and Hakan Johanson, “ Implementation of polyphase decomposed FIR filters for interpolation and decimation using multiple constant multiplication techniques”, IEEE Asia Pasific conference on circuits and systems, pp. 924-927, 2006.
  4. Jeffrey P. Long and Jose A. Torres, “ High Throughput Farrow Re-samplers Utlizing Reduced Complexity FIR Filters”, IEEE International Conference on military communication, pp. 1-6, 2012.
  5. Gordana Jovanovic Dolecek, and Naina Rao Nagrale, “On Multiplier less fir decimation filter design,” IEEE Conference on Electronics, Circuits and Systems, pp. 967-970, 2007.
  6. Bregovic, R.; Yong Ching Lim; Saramaki, T., “Frequency Response Masking Based Design of Two-Channel FIR Filterbanks with Rational Sampling Factors and Reduced Implementation Complexity”, IEEE International Conference on Image and Signal Processing and Analysis, pp. 121-126, 2005.
  7. G. Molina Salgado, and G. Jovanovic Dolecek, “Nonrecursive comb decimation filter with an improved alias
  8. rejection,” IEEE Latin America Symposium on Circuits andSystems, pp.1-4, 2012.Robert Bregovic, Tapio Saramaki, Ya Jun Yu, and Yong Ching Lim, “An Efficient Implementation of Linear-Phase FIR Filters for a Rational Sampling Rate Conversion”, IEEE International Conference on circuits and systems, pp. 453- 498, 2006.
  9. Rajesh Mehra, Swapna Devi, “FPGA Based Design of High Performance Decimator using DALUT Algorithm”, ACEEE International Journal on Signal and Image Processing, Volume 1, pp. 9-13, 2010.
  10. Rajesh Mehra, and Lajwanti Singh, “cost analysis and simulation of decimator for multirate applications,” International Journal of Computers & Technology, vol. 11, no. 1, pp.2175-2181, 2013
  11. Rajesh Mehra and Rashmi Arora, “FPGA-Based Design of High Speed CIC Decimator for Wireless Applications”, International Journal of Advanced Computer Science and Applications, Vol. 2, No.5,pp. ,2011.
  12. Rajesh Mehra and Swapna Devi, “Efficient Hardware Co-Simulation of Down Converter for Wireless Communication Sysrems”, International Journal of VLSI Design and communication Systems, Volume 1, No. 2, pp. ,June 2010.
  13. Rajesh Mehra and Ravinder kaur, “Reconfigurable Area and Speed Efficient Interpolator using DALUT Algorithm”, Advanced in Networks and Communications, Volume 132, pp.117-125, 2011.
  14. Rajesh Mehra , “FPGA Design of Optimized CIC Interpolator for DSP Based Wireless Communication System”, IMS MANTHAN Journal of Mgt., Computer Science and Journalism, Volume 5, Issue-2, pp. 43-46, 2010.
  15. Rajesh Mehra and Swapna Devi “Optimized Design of Decimator for Alias Removal in Multirate DSP applications”, Nonlinear System and Wavelet Analysis, pp. 100-103, 2010
  16. Robert Bregovic, Ya JunYu, Tapio Saramaki, “ Implementation of Linear-Phase FIR Filters for a Rational Sampling-Rate Conversion Utilizing the Coefficient Symmetry”, IEEE Transactions on circuits and systems, Vol. 58, No. 3, pp. 548-561, MARCH 2011.
  17. C-C Hasiao, “Polyphase filter matrix for rational sampling rate conversion”, IEEE International Conference on Speech, Signal Process, pp. 2173-2176, April 1987.
  18. Yong Ching Lim. "An Efficient Implementation of Linear-Phase FIR Filters for a Rational Sampling Rate Conversion", IEEE International Symposium onCircuits and Systems ISCAS-06, 2006.
Index Terms

Computer Science
Information Sciences

Keywords

FIR filter linear phase multirate system rational sampling rate conversion.