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Innovative Low Power Transposition Memory using Double Edge Triggered Flip-flop

by P. Vamshi Bhargava, G.V. Maha Lakshmi
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International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 128 - Number 4
Year of Publication: 2015
Authors: P. Vamshi Bhargava, G.V. Maha Lakshmi
10.5120/ijca2015906517

P. Vamshi Bhargava, G.V. Maha Lakshmi . Innovative Low Power Transposition Memory using Double Edge Triggered Flip-flop. International Journal of Computer Applications. 128, 4 ( October 2015), 28-32. DOI=10.5120/ijca2015906517

@article{ 10.5120/ijca2015906517,
author = { P. Vamshi Bhargava, G.V. Maha Lakshmi },
title = { Innovative Low Power Transposition Memory using Double Edge Triggered Flip-flop },
journal = { International Journal of Computer Applications },
issue_date = { October 2015 },
volume = { 128 },
number = { 4 },
month = { October },
year = { 2015 },
issn = { 0975-8887 },
pages = { 28-32 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume128/number4/22862-2015906517/ },
doi = { 10.5120/ijca2015906517 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-06T23:20:54.281470+05:30
%A P. Vamshi Bhargava
%A G.V. Maha Lakshmi
%T Innovative Low Power Transposition Memory using Double Edge Triggered Flip-flop
%J International Journal of Computer Applications
%@ 0975-8887
%V 128
%N 4
%P 28-32
%D 2015
%I Foundation of Computer Science (FCS), NY, USA
Abstract

Transposition memory (TRAM) is one of the most important matrix processing block. This paper presents the design of a transposition memory implemented using 1V 45nm CMOS technology in Cadence® Virtuoso® Design Environment. A new double edge triggered flip-flop based on clock-gated pulse suppression technique is developed. This new double edge triggered flip-flop evolved from clock-gating pulse suppression technique reduces the power dissipation in the clocking system. This new clock-gated pulse suppressed double edge triggered flip-flop (CGPSDFF) is used to design the D flip-flop based architecture of a high speed TRAM and power reduction of the CGPSDFF-based TRAM is 20% better than conventional TRAM.

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Index Terms

Computer Science
Information Sciences

Keywords

Low power TRAM clock system clock-gated pulse suppression technique CGPSDFF

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