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Performance Analysis of Branch Prediction Unit for Pipelined Processors
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 128 - Number 16 |
| Year of Publication: 2015 |
| Authors: Nikhil Panwar, Manjit Kaur, Gurmohan Singh |
10.5120/ijca2015906740
|
Nikhil Panwar, Manjit Kaur, Gurmohan Singh . Performance Analysis of Branch Prediction Unit for Pipelined Processors. International Journal of Computer Applications. 128, 16 ( October 2015), 6-12. DOI=10.5120/ijca2015906740
Abstract
The branch predictor plays a crucial role in the achievement of effective performance in microprocessors with pipelined architectures. This paper analyzes performance of branch prediction unit for pipelined processors. A memory of 512 bytes is designed for storing instructions. A 32 byte memory is designed for branch target buffer (BTB). This memory is utilized for storing history of the branch instructions. A Finite State Machine (FSM) is designed for branch predictor unit. It consists of four states: strongly taken, weakly taken, weakly not taken and strongly not taken. Prediction is done based on the status of FSM. If the state of FSM is weakly taken or strongly taken, then predictor guesses it as a taken condition else it is assumed to be not taken condition. When the execution of branch instruction is done for the first time the BTB stores the address of current instruction and also the address where it jumps. After this the current status of the FSM is updated accordingly. The program is executed using a branch predictor unit and also without a branch predictor unit. The latency of both the processors with a branch prediction unit and without is branch prediction unit is computed and compared. The simulation results validates that with branch prediction unit latency is decreased.
References
- H. Arora, S. Kotecha, R. Samyal, “Dynamic Branch Prediction Modeller for RISC Architecture,” in Proc. International Conf Machine Intelligence and Research Advancement (ICMIRA), pp.397-401, Dec. 21-23,2013.
- D. A. Patterson and J. L. Hennessy, Computer Organization and Design: The Hardware Software Interface. Burlington. 4th ed. USA: Morgan Kaufmann, 2010.
- D. Orozco, “TIDeFlow: A Parallel Execution Model for High Performance Computing Programs,” in Proc. International Conf Parallel Architectures and Compilation Techniques (PACT), pp.211-216, Oct. 10-14, 2011.
- C. Egan, “Dynamic Branch Prediction in High Performance Super Scalar Processors,” Ph.D. thesis, University of Hertfordshire, August 2000.
- Dezso Sima, Terence Fountain and Peter Kacsuk, Advanced Computer Architectures: A Design Space Approach. 1st edition Pearson Education Inc., 1997.
- Tse-Yu Yeh, “Two-Level Adaptive Branch Prediction and Instruction Fetch Mechanisms for High Performance Superscalar Processors,” PhD thesis, University of Michigan., 1993.
- J.V Kumar, B Nagaraju, C Swapna, T Ramanjappa, “Design and development of FPGA based low power pipelined 64-Bit RISC processor with double precision floating point unit,” in Proc. International Conf Communications and Signal Processing (ICCSP)., pp.1054-1058, Apr. 3-5,2014.
- P.P Ravale, S. S Apte, “Design of a branch prediction unit of a microprocessor based on superscalar architecture using VLSI,” in Proc. 2nd International Conf Computer Engineering and Technology (ICCET), vol.3, pp.355-360, Apr. 16-18, 2010.
- J.W Kwak, C.S Jhon, “High-performance embedded branch predictor by combining branch direction history and global branch history,” in Proc. IET Computers & Digital Techniques, vol.2, no.2, pp.142-154, March 2008.
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