CFP last date
20 December 2024
Reseach Article

Galois Field based Montgomery Multiplier for RSA Cryptosystem using Area Efficient Adder

by Ritu Gupta, Kavita Khare
International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 127 - Number 3
Year of Publication: 2015
Authors: Ritu Gupta, Kavita Khare
10.5120/ijca2015906353

Ritu Gupta, Kavita Khare . Galois Field based Montgomery Multiplier for RSA Cryptosystem using Area Efficient Adder. International Journal of Computer Applications. 127, 3 ( October 2015), 35-37. DOI=10.5120/ijca2015906353

@article{ 10.5120/ijca2015906353,
author = { Ritu Gupta, Kavita Khare },
title = { Galois Field based Montgomery Multiplier for RSA Cryptosystem using Area Efficient Adder },
journal = { International Journal of Computer Applications },
issue_date = { October 2015 },
volume = { 127 },
number = { 3 },
month = { October },
year = { 2015 },
issn = { 0975-8887 },
pages = { 35-37 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume127/number3/22712-2015906353/ },
doi = { 10.5120/ijca2015906353 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-06T23:19:22.598268+05:30
%A Ritu Gupta
%A Kavita Khare
%T Galois Field based Montgomery Multiplier for RSA Cryptosystem using Area Efficient Adder
%J International Journal of Computer Applications
%@ 0975-8887
%V 127
%N 3
%P 35-37
%D 2015
%I Foundation of Computer Science (FCS), NY, USA
Abstract

Data security is the major point of concern in today’s internet communication system for which cryptography plays a vital role. Modular multiplier plays a key role in modern cryptography system. Galois field arithmetic is being popularly used in such applications. Montgomery multiplication is the method for boosting up the speed of modular multiplication. Montgomery modular multiplier is implemented for larger operand size to design encryption and decryption algorithm for RSA security system. This paper contributes to the implementation of modular multiplier using Montgomery algorithm for RSA encryption and decryption ,where existing architecture is implemented using carry select adder and modified carry select adder and it is concluded that later uses 23% less area and approximate 4.5% less output delay as compared to former, in VHDL using Xilinx ISE 9.2i and has been simulated on FPGA device spartan3, xc3s200-5ft256.

References
  1. Peter L. Montgomery, “Modular Multiplication without trial division”, Mathematics of computation,44(170):519-521,1985.
  2. R.L. Rivest , A.Shamir and L.Adleman, “A Method for obtaining digital signature and public key cryptosystem”, Communication of ACM, vol.21, pp.120-126,February 1978.
  3. E. F. Brickel, “A fast modular multiplication algorithm with application to two key cryptography” in Advances in Cryptography – CRYPTO '82, Plenum, New York, pages 51–60, 1983.
  4. S.kakde,S.Baswaik,Y.Deodhe, “Power analysis of Montgomery Modular multiplier for Cryptosystem”,ICMIRA,2013,IEEE.
  5. W.Diffie and M.Hellmen, “new directions in cryptography”,IEEE transaction on information technology,vol.22 pp.644-654, November 1976.
  6. G.R.Blakley, “ A computer algorithm for the product of AB modulo M”, IEEE transaction on computers, vol.32,no.5 pp.497-500, may 1983.
  7. Basant kumar Mohanty, senior member IEEE, and Sujit kumar patel, “Area-delay-power effi-cient Carry select adder”, IEEE transaction on circuit and system-II, vol.61,no.6, june 2014.
  8. Huapeng wu, “Efficient bit-serial finite field montgomery multiplier in GF(2m)”, 4th IEEE International Conference on Information and technology (ICIST), pp. 527-530, april 2014.
  9. Aswathy B.G, Resmi R, “Modified RSA Public key Algorithm”, Internatonal conference on computational systems and communications(ICCSC), pp.252-255, December-2014.
  10. I.-C. Wey, C.-C. Ho, Y.-S. Lin, and C. C. Peng, “An area-efficient carry select adder design by sharing the common Boolean logic term,” in Proc. IMECS, pages 1–4, 2012.
  11. Jayanthi,A.N; Ravichandran, C.S, “Comparison of performance of high speed VLSI adders”, International Conference on Current Trends in Engineering and Technology (ICCTET), pages 99-104, 2013.
  12. Mahalakshmi.R, Sasilatha.T, “A power efficient carry save adder and modified carry saver adder using CMOS technology”, IEEE International conference on computational intelligence and computing research (ICCIC), pages 1-5, 2013.
Index Terms

Computer Science
Information Sciences

Keywords

Carry select adder Montgomery algorithm RSA cryptography modular arithmetic.