CFP last date
20 December 2024
Call for Paper
January Edition
IJCA solicits high quality original research papers for the upcoming January edition of the journal. The last date of research paper submission is 20 December 2024

Submit your paper
Know more
The week's pick
Responsive image
Improved Shuffled Frog Leaping Algorithm with Self-Adaptive Shuffling for Fuzzy Logic PD+G Controller Optimization in Robotic Manipulators

Duc Hoang Nguyen
Random Articles
Reseach Article

FPGA Implementation of 4-Point and 8-Point Fast Hadamard Transform

by Ankit Agrawal, Rakesh Bairathi, Amit Joshi
journal cover thumbnail

International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 124 - Number 3
Year of Publication: 2015
Authors: Ankit Agrawal, Rakesh Bairathi, Amit Joshi
10.5120/ijca2015904528

Ankit Agrawal, Rakesh Bairathi, Amit Joshi . FPGA Implementation of 4-Point and 8-Point Fast Hadamard Transform. International Journal of Computer Applications. 124, 3 ( August 2015), 23-28. DOI=10.5120/ijca2015904528

@article{ 10.5120/ijca2015904528,
author = { Ankit Agrawal, Rakesh Bairathi, Amit Joshi },
title = { FPGA Implementation of 4-Point and 8-Point Fast Hadamard Transform },
journal = { International Journal of Computer Applications },
issue_date = { August 2015 },
volume = { 124 },
number = { 3 },
month = { August },
year = { 2015 },
issn = { 0975-8887 },
pages = { 23-28 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume124/number3/22084-2015904528/ },
doi = { 10.5120/ijca2015904528 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-06T23:13:25.532922+05:30
%A Ankit Agrawal
%A Rakesh Bairathi
%A Amit Joshi
%T FPGA Implementation of 4-Point and 8-Point Fast Hadamard Transform
%J International Journal of Computer Applications
%@ 0975-8887
%V 124
%N 3
%P 23-28
%D 2015
%I Foundation of Computer Science (FCS), NY, USA
Abstract

Transformation is one of the fundamental blocks of many signal processing applications. The Hadamard transform is useful in variety of application including  data encryption methods and latest data compression algorithms such as JPEG extended range (JPEG XR), High Efficiency Video Coding (HEVC) etc. Hadamard transform is multiplier less technique and requires additions and subtractions only. In this paper, we have proposed an efficient method of 4 and 8 points Hadamard transformation using a parallel processing to achieve higher speed. The 8-point DHT has been realized with 4 points DHT implementation. The modules are synthesized using Xilinx ISE 14.2 software with the usage of inbuilt memory core generator for storing co-efficient values. The performance has been verified with area and timing analysis. The proposed implementation shows excellent results and also compared to previous works.

References
  1. Fan, Chih-Peng, Chia-Wei Chang, and Shun-Ji Hsu. "Cost-Effective Hardware-Sharing Design of Fast Algorithm Based Multiple Forward and Inverse Transforms for H. 264/AVC, MPEG-1/2/4, AVS, and VC-1 Video Encoding and Decoding Applications." Circuits and Systems for Video Technology, IEEE Transactions on 24, no. 4 (2014): 714-720.
  2. Joshi, Amit M., Vivekanand Mishra, and R. M. Patrikar. "Design of real-time video watermarking based on Integer DCT for H. 264 encoder." International Journal of Electronics 102, no. 1 (2015): 141-155.
  3. Rosenfeld, Azriel, and Avinash C. Kak. Digital picture processing. Vol. 1. Elsevier, 2014.
  4. Joshi, Amit M., Vivekanand Mishra, and R. M. Patrikar. "FPGA prototyping of video watermarking for ownership verification based on H. 264/AVC."Multimedia Tools and Applications (2015): 1-24.
  5. Joshi, A., Mishra, V., & Patrikar, R. M., “Real Time Implementation of Digital Watermarking Algorithm for Image and Video Application,” InTech, Watermarking/Book2, 2012,pp.64-88.
  6. J. Jurczyk and K. Loparo, ll~athematicatlr ansforms and correlation techniques for object recognition using tactile data," IEEE Transactions on Robotics and ~utomation, vol. 5, No.3, June 1989, pp. 359-362.
  7. Meher, Pramod Kumar, and Jagdish Chandra Patra. "Fully-pipelined efficient architectures for FPGA realization of discrete Hadamard transform." InApplication-Specific Systems, Architectures and Processors, 2008. ASAP 2008. International Conference on, pp. 43-48. IEEE, 2008.
  8. Amira, Abbes, and Shrutisagar Chandrasekaran. "Power modeling and efficient FPGA implementation of FHT for signal processing." Very Large Scale Integration (VLSI) Systems, IEEE Transactions on 15, no. 3 (2007): 286-295.
  9. Porto, M. S., T. L. Da Silva, R. E. C. Porto, L. V. Agostini, I. V. da Silva, and S. Bampi. "Design space exploration on the H. 264 4× 4 Hadamard transform." In NORCHIP Conference, 2005. 23rd, pp. 188-191. IEEE, 2005.
  10. Bernhard, Michael, and Joachim Speidel. "Multicarrier Transmission using Hadamard Transform for Optical Communications." ITG-Fachbericht-Photonische Netze (2013).
  11. Amira, A., A. Bouridane, P. Milligan, and M. Roula. "Novel FPGA implementations of Walsh–Hadamard transforms for signal processing." IEE Proceedings-Vision, Image and Signal Processing 148, no. 6 (2001): 377-383.
  12. Sridevi, J., J. E. N. Abhilash, and J. Vasanta Kumar. "Implementation Of Fully-Pipelined 16-Point DHT Architectures Using 8-Point And 4-Point DHTs for FPGA Realization." International Journal of Advanced Research in Computer Engineering & Technology (IJARCET) 1.9 (2012):pp-256.
Index Terms

Computer Science
Information Sciences

Keywords

Distributed memory Frequency domain Real time implementation Reconfiguarble Synthesize.

Powered by PhDFocusTM