The week's pick
Reseach Article
Static Power Reduction in 32-bit Ripple Carry Adder using Dual Threshold Voltage Assignment
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 124 - Number 2 |
| Year of Publication: 2015 |
| Authors: Md. Masood Ahmad, K. Manjunathachari, K. Lalkishore |
10.5120/ijca2015905366
|
Md. Masood Ahmad, K. Manjunathachari, K. Lalkishore . Static Power Reduction in 32-bit Ripple Carry Adder using Dual Threshold Voltage Assignment. International Journal of Computer Applications. 124, 2 ( August 2015), 16-20. DOI=10.5120/ijca2015905366
Abstract
Reduction in leakage power has become an important concern in low-voltage, low-power, and high-performance applications. In this paper, the dual-threshold technique is used to reduce leakage power in a 32-bit ripple carry adder by assigning high-threshold voltage to some transistors in noncritical paths, and using low-threshold transistors in critical path. The circuit was implemented using Cadence Virtuoso tools in 90-nm technology. The optimized layout of the ripple carry adder is designed using Cadence Virtuoso Layout Suite. Performance parameters such as total power, delay, static power and power delay product (PDP), were calculated and compared with the existing design topologies of full adder. The simulation results of the 32-bit ripple carry adder using the dual threshold voltage technique are compared with the conventional 32-bit ripple carry adder with different threshold values. Results show that the dual-threshold technique is good for leakage power reduction during runtime mode.
References
- J. M. Rabaey, Digital Integrated Circuits. Englewood Cliffs, NJ: Prentice-Hall, 1996.
- A. P. Chandrakasan, S. Sheng, and R. W. Brodersen, “Low-powerCMOS digital design,” IEEE J. Solid-State Circuits, vol. 27, p.473, Apr. 1992.
- S. Mutoh et. al., “1-V power supply high-speed digital circuit technology with multithreshold-voltage CMOS,” IEEE J. Solid-State Circuits, vol.30, pp. 847–854, Aug. 1995.
- J. Kao, A. Chandrakasan, and D. Antoniadis, “Transistor sizing issues and tool for multi-threshold CMOS technology,” in ACM/IEEE Design Automation Conf., 1997.
- L. Wei, Z. Chen, K. Roy, M. C. Johnson, Y. Ye, and V. K. De. ”Design and Optimization of Dual-threshold Circuitsfor Low-voltage Low-power Applications.” IEEE TVLSI, 7(1):16–24, March 1999.
- P. Pant, R. K. Roy, and A. Chatterjee. “Dual-threshold Voltage Assignment with Transistor Sizing for Low Power CMOS Circuits”. IEEE TVLSI, 9(2):390–394, April 2001.
- J. D. Meindl, “Low power microelectronics: Retrospect and prospect,”Proc. IEEE, vol. 83, p. 619, Apr. 1995.
- J. Sheu, et al., “BSIM: Berkeley Shortchannel IGFET Model for MOS transistors”, August 1987.
- N. H. E. Weste, and K. Eshraghian, “Principles of CMOS VLSI Design: A Systems Perspective, 2”d ed.”, Addison Wesley, 1995.
- Roy, S. ; Dept. of Comput. Sci. & Eng., Indian Inst. of Technol. Kharagpur, Kharagpur ; Pal, A., “Impact of runtime leakage reduction techniques on delay and power sensitivity under effective channel length variations” TENCON 2008 - 2008 IEEE Region 10 Conference Nov. 2008
- HeungJun Jeon,Yong-Bin Kim, Minsu Choi, “Standby Leakge Power Reduction Technique for Nanoscale CMOS VLSI systems” IEEE TIM, 1127-1133, May 2010
Index Terms
Keywords