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Static Power Reduction in 32-bit Ripple Carry Adder using Dual Threshold Voltage Assignment

by Md. Masood Ahmad, K. Manjunathachari, K. Lalkishore
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International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 124 - Number 2
Year of Publication: 2015
Authors: Md. Masood Ahmad, K. Manjunathachari, K. Lalkishore
10.5120/ijca2015905366

Md. Masood Ahmad, K. Manjunathachari, K. Lalkishore . Static Power Reduction in 32-bit Ripple Carry Adder using Dual Threshold Voltage Assignment. International Journal of Computer Applications. 124, 2 ( August 2015), 16-20. DOI=10.5120/ijca2015905366

@article{ 10.5120/ijca2015905366,
author = { Md. Masood Ahmad, K. Manjunathachari, K. Lalkishore },
title = { Static Power Reduction in 32-bit Ripple Carry Adder using Dual Threshold Voltage Assignment },
journal = { International Journal of Computer Applications },
issue_date = { August 2015 },
volume = { 124 },
number = { 2 },
month = { August },
year = { 2015 },
issn = { 0975-8887 },
pages = { 16-20 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume124/number2/22076-2015905366/ },
doi = { 10.5120/ijca2015905366 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-06T23:13:20.669527+05:30
%A Md. Masood Ahmad
%A K. Manjunathachari
%A K. Lalkishore
%T Static Power Reduction in 32-bit Ripple Carry Adder using Dual Threshold Voltage Assignment
%J International Journal of Computer Applications
%@ 0975-8887
%V 124
%N 2
%P 16-20
%D 2015
%I Foundation of Computer Science (FCS), NY, USA
Abstract

Reduction in leakage power has become an important concern in low-voltage, low-power, and high-performance applications. In this paper, the dual-threshold technique is used to reduce leakage power in a 32-bit ripple carry adder by assigning high-threshold voltage to some transistors in noncritical paths, and using low-threshold transistors in critical path. The circuit was implemented using Cadence Virtuoso tools in 90-nm technology. The optimized layout of the ripple carry adder is designed using Cadence Virtuoso Layout Suite. Performance parameters such as total power, delay, static power and power delay product (PDP), were calculated and compared with the existing design topologies of full adder. The simulation results of the 32-bit ripple carry adder using the dual threshold voltage technique are compared with the conventional 32-bit ripple carry adder with different threshold values. Results show that the dual-threshold technique is good for leakage power reduction during runtime mode.

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Index Terms

Computer Science
Information Sciences

Keywords

Leakage power static power

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