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High Speed Area Efficient 32 Bit Wallace Tree Multiplier
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 124 - Number 13 |
| Year of Publication: 2015 |
| Authors: Keshaveni N. |
10.5120/ijca2015905742
|
Keshaveni N. . High Speed Area Efficient 32 Bit Wallace Tree Multiplier. International Journal of Computer Applications. 124, 13 ( August 2015), 25-28. DOI=10.5120/ijca2015905742
Abstract
A 32 bit high speed area efficient Wallace tree multiplier is designed using verilog HDL and implemented in FPGA. The circuit is designed using carry save adder architecture and finally with one look ahead carry adder. The design is an improved version of tree based Wallace tree multiplier architecture. This paper aims at high speed multiplication and an area efficient 32 bit Wallace tree multiplier. The entire design is coded in Verilog HDL, simulated with Modelsim and synthesized using Xilinx FPGA device. The result shows that the proposed architecture takes very less time for computing the multiplication of two 32 bit numbers. In terms of area also, the proposed multiplier is much efficient than the existing methods. The frequency of operation of the circuit is 200 MHz.
References
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