CFP last date
20 January 2025
Call for Paper
February Edition
IJCA solicits high quality original research papers for the upcoming February edition of the journal. The last date of research paper submission is 20 January 2025

Submit your paper
Know more
The week's pick
Responsive image
Implementation of Feature Selection Using Correlation Matrix in Python

Ahmad Farhan AlShammari
Random Articles
Reseach Article

A Review of VLSI Structure for the Implementation of Matrix Multiplication

by Ruchi Thakkar, Paresh Rawat
journal cover thumbnail

International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 123 - Number 4
Year of Publication: 2015
Authors: Ruchi Thakkar, Paresh Rawat
10.5120/ijca2015905298

Ruchi Thakkar, Paresh Rawat . A Review of VLSI Structure for the Implementation of Matrix Multiplication. International Journal of Computer Applications. 123, 4 ( August 2015), 38-42. DOI=10.5120/ijca2015905298

@article{ 10.5120/ijca2015905298,
author = { Ruchi Thakkar, Paresh Rawat },
title = { A Review of VLSI Structure for the Implementation of Matrix Multiplication },
journal = { International Journal of Computer Applications },
issue_date = { August 2015 },
volume = { 123 },
number = { 4 },
month = { August },
year = { 2015 },
issn = { 0975-8887 },
pages = { 38-42 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume123/number4/21951-2015905298/ },
doi = { 10.5120/ijca2015905298 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-06T23:11:49.372386+05:30
%A Ruchi Thakkar
%A Paresh Rawat
%T A Review of VLSI Structure for the Implementation of Matrix Multiplication
%J International Journal of Computer Applications
%@ 0975-8887
%V 123
%N 4
%P 38-42
%D 2015
%I Foundation of Computer Science (FCS), NY, USA
Abstract

Matrix multiplication is the kernel operation used in many transform, image processing and digital signal processing application. In this paper, we have studied for parallel-parallel input and single output (PPI-SO), parallel-parallel input and multiple output (PPI-MO) and parallel-parallel fixed input and multiple output (PFI-MO) matrix-matrix multiplication. It is also a well-known fact that the multiplier and adder unit forms an integral part of matrix multiplication. Due to this regard, high speed multiplier and adder become the need of the day. In this paper, we have studied of Vedic mathematics multiplier using compressors.

References
  1. T. Arslan, D.H. Horrocks, and A.T. Erdogan,“Overview and Design Directions for Low-Power Circuits and Architectures for Digital Signal Processing,” IEE Colloquium on Low Power Analog and Digital VLSI: ASICS, Techniques and Applications, pp. 6/1 – 6/5, 1995.
  2. Massoud Pedram, “Design Technologies for Low Power VLSI,” Encyclopedia of Computer Science and Technology, pp. 1 – 32,1995.
  3. O. Mencer, M. Morf, and M. J. Flynn, “ PAM-Blox: High performance FPGA design for adaptive computing,” in Field Programmable Custom Computing Machines (FCCM), pp. 167 – 174, 1998.
  4. K. K. Parhi, VLSI Digital Signal Processing Systems. John Wiley & Sons, Inc. 1999.
  5. A. Amira, A. Bouridane, and P. Milligan, “Accelerating matrix product on reconfigurable hardware for signal processing,” in Proceedings 11th International Conference on Field-Programmable Logic and Its Applications (FPL), pp. 101 – 111, 2001.
  6. S. Tugsinavisut, S. Jirayucharoensak and P. A. Beerelt, “An Asynchronous Pipeline Comparisonswith Applications to DCT Matrix-vector Multiplication,” in Proceedings of the 2003 International Symposium on Circuits and Systems(ISCAS), vol. 5, pp. V-361 - V-364, 2003.
  7. Ju-Wook Jang, Seonil B. Choi, and Viktor K. Prasanna,” Energy- and Time-Efficient Matrix Multiplication on FPGAs”, IEEE Transaction on Very Large Scale Integration (VLSI) Systems, vol. 13, no. 11, pp. 1305 – 1319, 2005.
  8. Song Sun, Madhu Monga, Phillip H. Jones, “An I/ O Bandwidth-Sensitive Sparse Matrix-Vector Multiplic Engine on FPGAs”, IEEE Transactions On Circuits And Systems—I: Regular Papers, Vol. 59, No. 1, January 2012.
  9. Shivangi Tiwari and Nitin Meena, “Efficient Hardware Design for Implementation of Matrix Multiplication by using PPI-SO”, International Journal of Innovative Research in Computer and Communication Engineering Vol. 1, Issue 4, July 2013 ISSN (Online): 2320 – 9801.
  10. Shivangi Tiwari, Shweta Singh and Nitin Meena, “FPGA Design and Implementation of Matrix Multiplication Architecture by PPI-MO Techniques”, International Journal of Computer Applications (0975 – 8887)Volume 80 – No1, October 2013.
  11. Sushma R. Huddar and Sudhir Rao, “Novel High Speed Vedic Mathematics Multiplier using Compressors”, 978-1-4673-5090-7/13/$31.00 ©2013 IEEE.
Index Terms

Computer Science
Information Sciences

Keywords

Parallel-Parallel Input and Single Output (PPI-SO) Parallel-Parallel Input and Multiple Output (PPI-MO) Matrix Multiplication (MM)

Powered by PhDFocusTM