The week's pick
Reseach Article
Area Efficient Layout Design of CMOS Comparator using PTL Logic
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 122 - Number 16 |
| Year of Publication: 2015 |
| Authors: Jyoti, Rajesh Mehra |
10.5120/21784-5065
|
Jyoti, Rajesh Mehra . Area Efficient Layout Design of CMOS Comparator using PTL Logic. International Journal of Computer Applications. 122, 16 ( July 2015), 14-17. DOI=10.5120/21784-5065
Abstract
Comparator is a very useful combinational logic circuit. In this paper performance analysis of CMOS Comparator and PTL logic design has been shown. In the design of integrated circuits, several logic families is being used which is described by Pass Transistor Logic (PTL). It reduces the count of transistors used to make different logic gates, by eliminating redundant transistors. The layout of 2-bit comparator is developed using automatic and semi-custom techniques. Both the layouts are compared and analyzed in terms of their area consumption. Automatic layout is generated from its equivalent schematic whereas semi-custom layout is optimized manually. The result shows that semi-custom layout of PTL logic consumes 35% less area as compared to CMOS logic design to provide area efficient solution.
References
- Tanvi Sood, Rajesh Mehra, " Design a Low Power Half-Subtractor Using . 90?m CMOS Technology" IOSR Journal of VLSI and Signal Processing, Vol. 2, Issue 3, pp. 51-56, 2013.
- Samaneh Babayan-Mashhadi and Reza Lotfi, " Analysis & Design of a Low Voltage Low-Power Double-Tail Comparator" IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 22, No. 2, pp. 343-352, 2014.
- Vandana Choudhary, Rajesh Mehra, " 2- Bit Comparator Using Different Logic Style of Full Adder" International Journal of soft Computing and Engineering, Vol. 3, Issue 2, pp. 277-279, 2013.
- Prashant Upadhyay, Mr. Rajesh Mehra, Niveditta Thakur, "Low Power Design of an SRAM Cell for Portable Devices" International Conference on Computer & Communication Technology, pp. 255-259, 2010.
- Pushpa Saini, Rajesh Mehra, "A Novel Technique for Glitch and Leakage Power Reduction in CMOS VLSI Circuits", International Journal of Advanced Computer Science and Applications, Vol. 3, No. 10,pp. 161-168, 2012.
- Pushpa Saini, Rajesh Mehra, "Leakage Power Reduction in CMOS VLSI Circuits" International Journal of Computer Applications, Vol. 55, No. 8,pp. 42-48, 2012.
- Prashant Upadhyay, Rajesh Mehra, "Low Power Design of 64-bits Memory by using 8-T Proposed SRAM Cell", International Journal of Research and Reviews in Computer Science, Volume 1, pp. 168-172, 2010.
- N. West and K. Eshraghian 1993. "Principles of CMOS VLSI Design: a system perspective, Addison-Wesley Longman, 2nd Edition.
- C. -C. Wang, C. -F. Wu and K. -C. Tsai, "1-GHz 64-b high-speed comparator using ANT dynamic logic with two- phase clocking," IEE Proceeding , Computer & Digital Techniques, Vol. 145, No. 6, pp. 433–436, 2002.
- R. X. Gu and M. I. Elmasry, "All-N-Logic high-speed true-single-phase dynamic CMOS logic," IEEE J. Solid- State Circuits, Vol. 31, Issue 2, pp. 221–229, 2002.
- S. Furber, 1997 "ARM System Architecture", Addison-Wesley, 2nd Edition.
- J. -S. Wang and C. -H. Huang, "High-speed and low-power CMOS priority encoders," IEEE Journal of Solid-State Circuits, Vol. 35,Issue 10, pp. 1511–1514,2000.
- Anjuli, Satyajit Anand, " 2-Bit Magnitude Comparator Design Using different Logic Styles" International Journal of Engineering Science Invention,Vol. 2, Issue 1,pp. 13-24, 2013.
- M. Morris Mano, 2002 "Digital Design" Pearson Education Asia. 3rd Ed.
- A. Bellaouar and Mohamed I. Elmasry, 1995 "Low Power Digital VLSI Design: Circuits and Systems", Kluwer Academic Publishers, 2nd Ed.
- S. Salivahanan and S. Arivazhagan, 2004 "Digital Circuits and Design",2nd Ed.
Index Terms
Keywords