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A Study of Optimization Techniques for 3D Networks-on-Chip Architectures for Low Power and High Performance Applications

by Michael Opoku Agyeman
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International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 121 - Number 6
Year of Publication: 2015
Authors: Michael Opoku Agyeman
10.5120/21541-4531

Michael Opoku Agyeman . A Study of Optimization Techniques for 3D Networks-on-Chip Architectures for Low Power and High Performance Applications. International Journal of Computer Applications. 121, 6 ( July 2015), 1-8. DOI=10.5120/21541-4531

@article{ 10.5120/21541-4531,
author = { Michael Opoku Agyeman },
title = { A Study of Optimization Techniques for 3D Networks-on-Chip Architectures for Low Power and High Performance Applications },
journal = { International Journal of Computer Applications },
issue_date = { July 2015 },
volume = { 121 },
number = { 6 },
month = { July },
year = { 2015 },
issn = { 0975-8887 },
pages = { 1-8 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume121/number6/21541-4531/ },
doi = { 10.5120/21541-4531 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-06T23:09:20.964386+05:30
%A Michael Opoku Agyeman
%T A Study of Optimization Techniques for 3D Networks-on-Chip Architectures for Low Power and High Performance Applications
%J International Journal of Computer Applications
%@ 0975-8887
%V 121
%N 6
%P 1-8
%D 2015
%I Foundation of Computer Science (FCS), NY, USA
Abstract

Three dimensional Networks-on-Chip (3D NoCs) have attracted a growing interest to solve on-chip communication demands of future multi-core embedded systems. However, 3D NoCs have not been completely accepted into the mainstream due to issues such as the high cost and complexity of manufacturing 3D vertical wires, larger memory, area and power consumption of 3D NoC components than that of conventional 2D NoC. This paper presents a brief about 3D NoCs optimization techniques with focus on modeling and evaluation of alternate NoC topologies, routing algorithms and mapping techniques to achieve optimized area, power and performance parameters (latency and throughput). Particularly, we investigate novel 3D NoC router architectures and their possible combinations which aim at achieving lower area and power consumption of on-chip communication components with a minimal performance trade-off.

References
  1. P. P. Pande, C. Grecu, M. Jones, A. Ivanov, and R. Saleh, "Performance evaluation and design trade-offs for network-on-chip interconnect architectures," IEEE Transactions on Computers, vol. 54, no. 8, pp. 1025–1040, 2005.
  2. E. Salminen, A. Kulmala, and T. D. Hmlinen, "Survey of Network-on-chip Proposals," White paper OCP-IP, vol. 1, 2008.
  3. I. Loi, F. Angiolini, and L. Benini, "Supporting vertical links for 3D networks-on-chip: toward an automated design and analysis flow," in Proc. of the 2nd international conference on Nano-Networks, 2007, pp. 1 – 5.
  4. G. D. Micheli and L. Benini, Networks on Chips: Technology and Tools. Morgan Kaufmann, First Edition, 2006.
  5. V. Pavlidis and E. Friedman, "3-D Topologies for Networks-on-Chip," IEEE Trans. on Very Large Scale Integration (VLSI) Systems, vol. 15, no. 10, pp. 1081–1090, 2007.
  6. B. Feero and P. P. Pande, "Performance Evaluation for Three-Dimensional Networks-On-Chip," in Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2007, pp. 305–310.
  7. C. Addo-Quaye, "Thermal-aware mapping and placement for 3-D NoC designs," 2005, pp. 25–28.
  8. J. Kim, C. Nicopoulos, D. Park, R. Das, Y. Xie, V. Narayanan, M. S. Yousif, and C. R. Das, "A novel dimensionally-decomposed router for on-chip communication in 3D architectures," SIGARCH Comput. Archit. News, vol. 35, no. 2, pp. 138–149, 2007.
  9. S. Lim, "Physical design for 3D system on package," Design Test of Computers, IEEE, pp. 532–539, 2005.
  10. C. Seiculescu, S. Murali, L. Benini, and G. De Micheli, "SunFloor 3D: A tool for Networks On Chip topology synthesis for 3D systems on chips," 2009, pp. 9–14.
  11. K. Siozios, A. Bartzas, and D. Soudris, "Three dimensional network-on-chip architectures," in Networks-on-Chips: Theory and Practice, H. E. Fayez Gebali and M. W. El-Kharashi, Eds. CRC Press, 2009, pp. 1–28.
  12. S. Stergiou, F. Angiolini, S. Carta, L. Raffo, D. Bertozzi, and G. D. Micheli, "Xpipes Lite: A synthesis oriented design library for networks on chips," in Design, Automation and Test in Europe (DATE). IEEE, 2005, pp. 1188–1193.
  13. R. Marculescu, U. Ogras, L. -S. Peh, N. Jerger, and Y. Hoskote, "Outstanding research problems in noc design: System, microarchitecture, and circuit perspectives," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 28, no. 1, pp. 3 –21, 2009.
  14. S. K. Lee, C. Y. Kang, P. Kirsch, S. Arkalqud, R. Jammy, and B. H. Lee, "Comprehensive study for rf interference limited 3d tsv optimization," in International Symposium on VLSI Technology, Systems, and Applications (VLSI-TSA), 2013, pp. 1–2.
  15. P. C. Chew, L. Li, J. Xue, and W. Eklow, "Through silicon via (tsv) redundancy - a high reliability, networking product perspective," in International Conference on Electronic Materials and Packaging (EMAP), 2012, pp. 1–5.
  16. V. F. Pavlidis and E. G. Friedman, Three-dimensional Integrated Circuit Design. Morgan Kaufmann Publishers Inc. , 2009.
  17. B. Feero and P. Pande, "Networks-on-Chip in a Three-Dimensional Environment: A Performance Evaluation," IEEE Transactions on Computers, vol. 58, no. 1, pp. 32 –45, 2009.
  18. R. Patti, "Three-dimensional integrated circuits and the future of system-on-chip designs," Proceedings of the IEEE, vol. 94, no. 6, pp. 1214 –1224, 2006.
  19. S. K. Lim, "TSV-Aware 3D Physical Design Tool Needs for Faster Mainstream Acceptance of 3D ICs," ACM DAC Knowledge Center (dac. com), 2010.
  20. D. Velenis, M. Stucchi, E. Marinissen, B. Swinnen, and E. Beyne, "Impact of 3d design choices on manufacturing cost," in IEEE International Conference on 3D System Integration (3DIC), 2009, pp. 1 – 5.
  21. C. Feng, M. Zhang, J. Li, J. Jiang, Z. Lu, and A. Jantsch, "A low-overhead fault-aware deflection routing algorithm for 3d network-on-chip," in IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2011, pp. 19–24.
  22. C. Liu, L. Zhang, Y. Han, and X. Li, "Vertical interconnects squeezing in symmetric 3D mesh Network-on-Chip," in Asia and South Pacific Design Automation Conference (ASP-DAC), 2011, pp. 357 –362.
  23. "Tour guide to 3d-ic design tools and services," http://www. gsaglobal. org/eda/docs/, 2012, online; accessed June-2012.
  24. I. T. R. for Semiconductors (ITRS), http://www. itrs. net/, 2013, [Online; accessed February].
  25. G. H. Loh, Y. Xie, and B. Black, "Processor design in 3d die-stacking technologies," IEEE-Micro, vol. 27, pp. 31 –48, 2007.
  26. D. H. Kim, S. Mukhopadhyay, and S. K. Lim, "Through-silicon-via aware interconnect prediction and optimization for 3d stacked ics," in International workshop on System level interconnect prediction, 2009, pp. 85–92.
  27. D. H. Kim, S. Mukhopadhyay, and S. -K. Lim, "Tsv-aware interconnect length and power prediction for 3d stacked ics," in IEEE International Interconnect Technology Conference (IITC), 2009, pp. 26–28.
  28. D. H. Kim, K. Athikulwongse, and S. -K. Lim, "A study of through-silicon-via impact on the 3d stacked ic layout," in IEEE/ACM International Conference on Computer-Aided Design - Digest of Technical Papers (ICCAD). , 2009, pp. 674–680.
  29. R. Weerasekera, L. -R. Zheng, D. Pamunuwa, and H. Tenhunen, "Extending systems-on-chip to the third dimension: performance, cost and technological tradeoffs," in IEEE/ACM international conference on Computer-aided design (ICCAD), 2007, pp. 212–219.
  30. A. K. Mishra, N. Vijaykrishnan, and C. R. Das, "A case for heterogeneous on-chip interconnects for CMPs," in Annual International Symposium on Computer Architecture (ISCA), 2011, pp. 389–400.
  31. M. Al Faruque and J. Henkel, "Minimizing virtual channel buffer for routers in on-chip communication architectures," in Design, Automation and Test in Europe (DATE), march 2008, pp. 1238 –1243.
  32. A. Sharifi and H. Sarbazi-Azad, "Power consumption and performance analysis of 3d nocs," in Asia-Pacific Computer Systems Architecture Conference, 2007, pp. 209–219.
  33. T. Xu, P. Liljeberg, and H. Tenhunen, "A study of Through Silicon Via impact to 3D Network-on-Chip design," in 2010 International Conference On Electronics and Information Engineering (ICEIE), 2010, pp. 333 – 337.
  34. F. Li, C. Nicopoulos, T. Richardson, Y. Xie, V. Narayanan, and M. Kandemir, "Design and Management of 3D Chip Multiprocessors Using Network-in-Memory," in International Symposium on Computer Architecture (ISCA), 2006, pp. 130–141.
  35. M. O. Agyeman, A. Ahmadinia, and A. Shahrabi, "Heterogeneous 3d network-on-chip architectures: area and power aware design techniques," Journal of Circuits, Systems and Computers, vol. 22, no. 4, p. 1350016, 2013.
  36. ——, "Low power heterogeneous 3d networks-on-chip architectures," in International Conference on High Performance Computing and Simulation (HPCS), 2011, pp. 533 –538.
  37. M. O. Agyeman and A. Ahmadinia, "Optimising heterogeneous 3d networks-on-chip," in PARELEC, 2011, pp. 25–30.
  38. H. Ying, A. Jaiswal, T. Hollstein, and K. Hofmann, "Deadlock-free generic routing algorithms for 3-dimensional networks-on-chip with reduced vertical link density topologies," Journal of Systems Architecture, vol. 59, no. 7, pp. 528 – 542, 2013.
  39. A. -M. Rahmani, K. Latif, P. Liljeberg, J. Plosila, and H. Tenhunen, "A stacked mesh 3d noc architecture enabling congestion-aware and reliable inter-layer communication," in Euromicro International Conference on Parallel, Distributed and Network-Based Processing (PDP), 2011, pp. 423 –430.
  40. M. O. Agyeman, A. Ahmadinia, and A. Shahrabi, "Efficient routing techniques in heterogeneous 3d networks-on-chip," Parallel Computing, vol. 39, no. 9, pp. 389–407, 2013.
  41. M. O. Agyeman and A. Ahmadinia, "An adaptive router architecture for heterogeneous 3d networks-on-chip," in International IEEE NORCHIP Conference, 2011, pp. 1 –4.
  42. D. Park, S. Eachempati, R. Das, A. K. Mishra, Y. Xie, N. Vijaykrishnan, and C. R. Das, "Mira: A multi-layered on-chip interconnect router architecture," in Annual International Symposium on Computer Architecture, 2008, pp. 251–261.
  43. S. Pasricha, "Exploring serial vertical interconnects for 3d ics," in ACM/IEEE Design Automation Conference (DAC), 2009, pp. 581 –586.
  44. ——, "A framework for tsv serialization-aware synthesis of application specific 3d networks-on-chip," in International Conference on VLSI Design (VLSID), 2012, pp. 268 –273.
  45. W. Liwei, C. Yang, L. Xiaohui, and Z. Xiaohu, "Application specific buffer allocation for wormhole routing networks-on-chip," pp. 37–42, 2008.
  46. J. Hu, U. Y. Ogras, and R. Marculescu, "System-level buffer allocation for application-specific networks-on-chip router design," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 25, no. 12, pp. 2919 –2933, 2006.
  47. S. Foroutan, Y. Thonnart, R. Hersemeule, and A. Jerraya, "An analytical method for evaluating network-on-chip performance," in Design, Automation Test in Europe Conference Exhibition (DATE), march 2010, pp. 1629 –1632.
  48. A. S. Kumar, M. P. Kumar, S. Murali, V. Kamakoti, L. Benini, and G. D. Micheli, "A buffer-sizing algorithm for network-on-chips with multiple voltage-frequency islands," J. Electrical and Computer Engineering, vol. 2012, 2012.
  49. T. C. Xu, G. Schley, P. Liljeberg, M. Radetzki, J. Plosila, and H. Tenhunen, "Optimal placement of vertical connections in 3d network-on-chip," Journal of Systems Architecture, vol. 59, no. 7, pp. 441 – 454, 2013.
  50. M. O. Agyeman and A. Ahmadinia, "A systematic generation of optimized heterogeneous 3d networks-on-chip architecture," in NASA/ESA Conference on Adaptive Hardware and Systems (AHS), 2013, pp. 79–83.
  51. C. Ababei, H. S. Kia, O. P. Yadav, and J. Hu, "Energy and reliability oriented mapping for regular networks-on-chip," in NOCS, 2011, pp. 121–128.
  52. J. Hu and R. Marculescu, "Energy- and performance-aware mapping for regular NoC architectures," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 24, no. 4, pp. 551–562, 2005.
  53. X. Wang, M. Yang, Y. Jiang, and P. Liu, "A power-aware mapping approach to map ip cores onto nocs under bandwidth and latency constraints," TACO, vol. 7, no. 1, 2010.
  54. M. Janidarmian, A. Khademzadeh, and M. Tavanpour, "Onyx: A new heuristic bandwidth-constrained mapping of cores onto tile-based Network on Chip," Ieice Electronic Express, vol. 6, pp. 1–7, 2009.
  55. S. Tosun, "New heuristic algorithms for energy aware application mapping and routing on mesh-based nocs," Journal of Systems Architecture, vol. 57, no. 1, pp. 69 – 78, 2011.
  56. S. Murali and G. De Micheli, "Bandwidth-constrained mapping of cores onto NoC architectures," in Design, Automation and Test in Europe Conference and Exhibition (DATE), 2004, pp. 896 – 901.
  57. X. Wang, M. Palesi, M. Yang, Y. Jiang, M. C. Huang, and P. Liu, "Power-aware run-time incremental mapping for 3-d networks-on-chip," in NPC, 2011, pp. 232–247.
  58. C. -L. Chou and R. Marculescu, "Run-time task allocation considering user behavior in embedded multiprocessor networks-on-chip," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 29, no. 1, pp. 78 –91, 2010.
  59. M. Agyeman and A. Ahmadinia, "Optimised application specific architecture generation and mapping approach for heterogeneous 3d networks-on-chip," in IEEE International Conference on Computational Science and Engineering (CSE), 2013, pp. 794–801.
  60. M. M. Inc, http://www. micromagic. com, 2010, [Online; accessed July].
Index Terms

Computer Science
Information Sciences

Keywords

Network-on-Chip System-on-Chip 3D Integration Low Power

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