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A Study of Optimization Techniques for 3D Networks-on-Chip Architectures for Low Power and High Performance Applications

by Michael Opoku Agyeman
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International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 121 - Number 6
Year of Publication: 2015
Authors: Michael Opoku Agyeman
10.5120/21541-4531

Michael Opoku Agyeman . A Study of Optimization Techniques for 3D Networks-on-Chip Architectures for Low Power and High Performance Applications. International Journal of Computer Applications. 121, 6 ( July 2015), 1-8. DOI=10.5120/21541-4531

@article{ 10.5120/21541-4531,
author = { Michael Opoku Agyeman },
title = { A Study of Optimization Techniques for 3D Networks-on-Chip Architectures for Low Power and High Performance Applications },
journal = { International Journal of Computer Applications },
issue_date = { July 2015 },
volume = { 121 },
number = { 6 },
month = { July },
year = { 2015 },
issn = { 0975-8887 },
pages = { 1-8 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume121/number6/21541-4531/ },
doi = { 10.5120/21541-4531 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-06T23:09:20.964386+05:30
%A Michael Opoku Agyeman
%T A Study of Optimization Techniques for 3D Networks-on-Chip Architectures for Low Power and High Performance Applications
%J International Journal of Computer Applications
%@ 0975-8887
%V 121
%N 6
%P 1-8
%D 2015
%I Foundation of Computer Science (FCS), NY, USA
Abstract

Three dimensional Networks-on-Chip (3D NoCs) have attracted a growing interest to solve on-chip communication demands of future multi-core embedded systems. However, 3D NoCs have not been completely accepted into the mainstream due to issues such as the high cost and complexity of manufacturing 3D vertical wires, larger memory, area and power consumption of 3D NoC components than that of conventional 2D NoC. This paper presents a brief about 3D NoCs optimization techniques with focus on modeling and evaluation of alternate NoC topologies, routing algorithms and mapping techniques to achieve optimized area, power and performance parameters (latency and throughput). Particularly, we investigate novel 3D NoC router architectures and their possible combinations which aim at achieving lower area and power consumption of on-chip communication components with a minimal performance trade-off.

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Index Terms

Computer Science
Information Sciences

Keywords

Network-on-Chip System-on-Chip 3D Integration Low Power

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