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Implementation of Power Efficient Decoding Algorithm for LDPC Code

by Namrata H. Patel, Risha A Tiwari
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International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 120 - Number 22
Year of Publication: 2015
Authors: Namrata H. Patel, Risha A Tiwari
10.5120/21391-4434

Namrata H. Patel, Risha A Tiwari . Implementation of Power Efficient Decoding Algorithm for LDPC Code. International Journal of Computer Applications. 120, 22 ( June 2015), 13-17. DOI=10.5120/21391-4434

@article{ 10.5120/21391-4434,
author = { Namrata H. Patel, Risha A Tiwari },
title = { Implementation of Power Efficient Decoding Algorithm for LDPC Code },
journal = { International Journal of Computer Applications },
issue_date = { June 2015 },
volume = { 120 },
number = { 22 },
month = { June },
year = { 2015 },
issn = { 0975-8887 },
pages = { 13-17 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume120/number22/21391-4434/ },
doi = { 10.5120/21391-4434 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-06T23:06:53.074482+05:30
%A Namrata H. Patel
%A Risha A Tiwari
%T Implementation of Power Efficient Decoding Algorithm for LDPC Code
%J International Journal of Computer Applications
%@ 0975-8887
%V 120
%N 22
%P 13-17
%D 2015
%I Foundation of Computer Science (FCS), NY, USA
Abstract

Mobile computing devices like mobile, laptops& tablets that covered large market of end user facing battery issues is an open challenge for research scholars. In this project work I have attempt to optimize power [batteries relate issues] at decoding. Stare of most efficient error control LDPC code which is being used. In this work bit flipping decoder hard decision decoding is used which can be implemented by using 8 transistor by using XOR gate. This paper proposed 6 transistor XOR gate design and implemented which can be used in this decoder.

References
  1. R. G. Gallager, 'Low-Density Parity-Check Codes'. Cambridge,m. i. t. Press, 1962.
  2. A novel design of ultra low voltage energy efficient full adder,2014.
  3. A New Design of XOR-XNOR gates for low power application; Nabihah Ahmad, International Conference on Electronic Devices, (ICEDSA)2011
  4. FPGA Implementation of a LDPC Decoder Using a Reduced Complexity Message Passing Algorithm journal of networks,vol 6,no. 1,january 2011.
  5. Implementation for Two-Stage Hybrid Decoding for LDPC Codes;International Journal of Computer Applications Volume 80, October 2013.
  6. Efficient Encoding of Low-Density Parity-Check code /Thomas j. Richardson L,. Urbanke;IEEE,Vol47, No. 2,FEBRUARY 2001.
  7. LDPC Codes – a brief Tutorial,Bernhard M. J. Leiner, Stud. ID. :53418Lbleiner@gmail. com,April 8, 2005.
  8. Performance of QPSK-OFDM with LDPC & Concatenated Reed Solomon/Convolutional Coding in Outdoor Environments, ISSC, 2011.
  9. Introducing Low-Density Parity-Check, Codes,Sarah J. Johnson,School of Electrical Engineering and Computer Science,The University of Newcastle, Australia.
  10. Systematic construction, verification and implementation methodology for LDPC codes.
Index Terms

Computer Science
Information Sciences

Keywords

Decoding Encoding Low density parity check (LDPC) Bit flipping tanner graph XOR-XNOR.

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