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Design and Implementation of an Efficient 4G Digital down Converter used in Wireless Receiver Systems

by Shrita G, A R Aswatha
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International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 120 - Number 18
Year of Publication: 2015
Authors: Shrita G, A R Aswatha
10.5120/21327-4285

Shrita G, A R Aswatha . Design and Implementation of an Efficient 4G Digital down Converter used in Wireless Receiver Systems. International Journal of Computer Applications. 120, 18 ( June 2015), 17-20. DOI=10.5120/21327-4285

@article{ 10.5120/21327-4285,
author = { Shrita G, A R Aswatha },
title = { Design and Implementation of an Efficient 4G Digital down Converter used in Wireless Receiver Systems },
journal = { International Journal of Computer Applications },
issue_date = { June 2015 },
volume = { 120 },
number = { 18 },
month = { June },
year = { 2015 },
issn = { 0975-8887 },
pages = { 17-20 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume120/number18/21327-4285/ },
doi = { 10.5120/21327-4285 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-06T23:07:03.295076+05:30
%A Shrita G
%A A R Aswatha
%T Design and Implementation of an Efficient 4G Digital down Converter used in Wireless Receiver Systems
%J International Journal of Computer Applications
%@ 0975-8887
%V 120
%N 18
%P 17-20
%D 2015
%I Foundation of Computer Science (FCS), NY, USA
Abstract

A Digital Down Converter (DDC), which is basically used to convert an intermediate frequency (IF) signal to its baseband form, forms an integral part of wireless receivers. The major functional blocks of a DDC constitute a mixer, Numerically Controlled Oscillator (NCO) and an FIR filter chain. In this paper, an area efficient and high speed DDC has been designed and implemented. On comparison of the results with that of the existing methodology, the designed architecture achieves 44. 8% area efficiency and 80. 7% improvement in speed.

References
  1. Huddar, S. R. ; Rupanagudi, S. R. ; Kalpana, M. ; Mohan, S. , "Novel high speed vedic mathematics multiplier using compressors," Automation, Computing, Communication, Control and Compressed Sensing (iMac4s), 2013 International Multi-Conference on , vol. , no. , pp. 465,469, 22-23 March 2013
  2. Sushma R. Huddar, Sudhir Rao Rupanagudi, Venkatesh Janardhan, Surabhi Mohan, and S. Sandya, "Area and Speed Efficient Arithmetic Logic Unit Design Using Ancient Vedic Mathematics on FPGA," in Advances in Computing, Communication, and Control, pp. 475-483, Springer, Berlin Heidelberg, 2013.
  3. Huddar, S. R. ; Rupanagudi, Ramya R. ; Yadav S. ; Jan S. , "Novel Architecture for Inverse Mix Columns for AES using Ancient Vedic mathematics on FPGA," International Conference on advances in Computing, Communication and informatics (ICACCI). IEEE 2013.
  4. Qingxiang Zhang and Xiaoxiao Su, "The Design of Digital Down Converter Based on FPGA", Sch. Of Electron. & Inf. Eng. , Harbin Inst. Of Technol. , Harbin, China, September 2009.
  5. Mingxian Li, Lingyu Chen and Jiang Hong Shi, "Intermediate Frequency Design of Broadband Wireless Adhoc Network System", Dept. of Commun. Eng, Xiamen Univ. , Xiamen, China, August 2009.
  6. Lattice Semiconductor Corporation, "Multi-Channel Digital Up/Down Converter for WiMAX Systems", USA, April 2009.
  7. Sundarajan V and Parhi KK, "Synthesis of low power folded programmable coefficient FIR digital filters", Dept. of Electr. And Comput. Eng, Minnesota Univ. , Minneapolis, USA, June 2000.
Index Terms

Computer Science
Information Sciences

Keywords

DDC folded unfolded filter chain area speed

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