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A Novel Vedic Divider Architecture with Reduced Delay for VLSI Applications
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 120 - Number 17 |
| Year of Publication: 2015 |
| Authors: Siba Kumar Panda, Arati Sahu |
10.5120/21322-4350
|
Siba Kumar Panda, Arati Sahu . A Novel Vedic Divider Architecture with Reduced Delay for VLSI Applications. International Journal of Computer Applications. 120, 17 ( June 2015), 31-36. DOI=10.5120/21322-4350
Abstract
The ever increasing demand in VLSI architecture to handle complex systems has resulted for designing of high speed divider architecture. The divider is designed using ever known ancient methodology "Vedic mathematics". There are several methods present in Vedic mathematics but here Parvartya sutra is used. It is a general division formula which can be applicable to all cases of division which is an efficient way for dividing large numbers with respect to delay and power consumption. Here thirty-two bit divider architecture is implemented using this sutra & synthesized and simulated using Xilinx ISE simulator and implemented on virtex4 FPGA device XC4VLX15. The output parameters such as propagation delay and device utilization are calculated from synthesis results. Our result shows speed improvement as compared to other architecture presented in this literature. This architecture can be implemented in many applications such as digital signal processing, cryptography, processor arithmetic unit design etc.
References
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