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Equivalence Checking using Assertion based Technique
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 120 - Number 14 |
| Year of Publication: 2015 |
| Authors: Shailesh Kumar, Sameer Arvikar, Saurabh Jha, Tarun K. Gupta |
10.5120/21299-4349
|
Shailesh Kumar, Sameer Arvikar, Saurabh Jha, Tarun K. Gupta . Equivalence Checking using Assertion based Technique. International Journal of Computer Applications. 120, 14 ( June 2015), 39-43. DOI=10.5120/21299-4349
Abstract
This paper presents approach to equivalence checking methodology for large analog/mixed signal systems such as HDMI-PHY, USB-PHY (Transceiver). We verify the equivalence between a behavioral model and its electrical equivalent (Spice netlist) by applying same inputs to both representations. Inputs to spice are given through a D2A. The output waveforms are then compared to find the equivalence. We have implemented SystemVerilog assertions for critical timing checks. We are using digital-on-top (DoT) approach, SystemVerilog assertions are applied in the testbench, means the same assertions are applied to behavioral output as well as to the output of spice which is converted from analog to digital. We have given margin (rise/fall time) in assertions to ensure that assertion should comply with the allowed difference in spice and model output. The proposed methodology is then applied for equivalence checking of USB-PHY transceiver as a test case.
References
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