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A Genetic Algorithm based Two Phase Fault Simulator for Sequential Circuit

by Dhiraj Sangwan, Seema Verma, Rajesh Kumar
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International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 12 - Number 10
Year of Publication: 2011
Authors: Dhiraj Sangwan, Seema Verma, Rajesh Kumar
10.5120/1720-2311

Dhiraj Sangwan, Seema Verma, Rajesh Kumar . A Genetic Algorithm based Two Phase Fault Simulator for Sequential Circuit. International Journal of Computer Applications. 12, 10 ( January 2011), 17-24. DOI=10.5120/1720-2311

@article{ 10.5120/1720-2311,
author = { Dhiraj Sangwan, Seema Verma, Rajesh Kumar },
title = { A Genetic Algorithm based Two Phase Fault Simulator for Sequential Circuit },
journal = { International Journal of Computer Applications },
issue_date = { January 2011 },
volume = { 12 },
number = { 10 },
month = { January },
year = { 2011 },
issn = { 0975-8887 },
pages = { 17-24 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume12/number10/1720-2311/ },
doi = { 10.5120/1720-2311 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-06T20:01:18.132466+05:30
%A Dhiraj Sangwan
%A Seema Verma
%A Rajesh Kumar
%T A Genetic Algorithm based Two Phase Fault Simulator for Sequential Circuit
%J International Journal of Computer Applications
%@ 0975-8887
%V 12
%N 10
%P 17-24
%D 2011
%I Foundation of Computer Science (FCS), NY, USA
Abstract

Testing has become an important design step now days in digital circuit. A gate level fault simulation environment based on realistic fault models has been presented in this paper. A Genetic Algorithm (GA) is proposed which allows having fault simulation with conditional execution of test vector under 2 phase scheme. By using this approach a random search of test vectors is possible without being caught in a local minima or maxima. The award of fitness to the vector set allows having a selection of test vectors with high fault coverage and with large fault detection scores. Experimental results are provided which shows that the proposed technique can be employed for the detection of faults in a sequential circuit with high fault coverage.

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Index Terms

Computer Science
Information Sciences

Keywords

Genetic Algorithm Sequential Circuits Automatic Test Pattern Generator Fault coverage Circuit Under Test Flip-flop

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