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Power and Area Efficient Design of 6T Multiplexer using Transmission Gate Logic
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 119 - Number 6 |
| Year of Publication: 2015 |
| Authors: Priti Gupta, Rajesh Mehra |
10.5120/21073-3747
|
Priti Gupta, Rajesh Mehra . Power and Area Efficient Design of 6T Multiplexer using Transmission Gate Logic. International Journal of Computer Applications. 119, 6 ( June 2015), 23-26. DOI=10.5120/21073-3747
Abstract
The main issue in designing of VLSI circuits is power consumption and area requirement In this paper Multiplexer circuit is proposed with the help of transmission gate logic using 6 transistors. Different design methodologies are used for designing of multiplexer layout. Multiplexer is essential circuit for different field of network and communication. Multiplexer requires less number of transistors using transmission gate logic. The main concerned of this paper is to reduce area, power consumption and complexity of Multiplexer using different design methodologies.
References
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- K. Nehru, A. shanmugam Dr. , G. Darmila thenmozhi, " Design of Low powerALU using 8 T FA and PTL based MUX circuits",IEEE International Conference on advances in Engineering, Science and Management", pp. 145-149, March 2014.
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- Abdhesh Kumar Jha , Anshul Jain"Comparative Analysis of Demultiplexer using Different Logic Styles", International Journal for Scientific Research & Development, Vol. 2, Issue 12, 2015
- P. Upadhaya, Rajesh Mehra, "Low Power design of a SRAM cell for Portable Devices", IEEE International Conference on Computer and Communication Technology (ICCCT) , Vol. 10, pp. 255- 259, 2010.
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