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Study of Power-Delay Characteristics of a Mixed-Logic-Style Novel Adder Circuit at 90nm Gate Length

by Parameshwara M. C., Srinivasaiah H. C.
International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 119 - Number 4
Year of Publication: 2015
Authors: Parameshwara M. C., Srinivasaiah H. C.
10.5120/21057-3706

Parameshwara M. C., Srinivasaiah H. C. . Study of Power-Delay Characteristics of a Mixed-Logic-Style Novel Adder Circuit at 90nm Gate Length. International Journal of Computer Applications. 119, 4 ( June 2015), 27-33. DOI=10.5120/21057-3706

@article{ 10.5120/21057-3706,
author = { Parameshwara M. C., Srinivasaiah H. C. },
title = { Study of Power-Delay Characteristics of a Mixed-Logic-Style Novel Adder Circuit at 90nm Gate Length },
journal = { International Journal of Computer Applications },
issue_date = { June 2015 },
volume = { 119 },
number = { 4 },
month = { June },
year = { 2015 },
issn = { 0975-8887 },
pages = { 27-33 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume119/number4/21057-3706/ },
doi = { 10.5120/21057-3706 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-06T23:03:10.916381+05:30
%A Parameshwara M. C.
%A Srinivasaiah H. C.
%T Study of Power-Delay Characteristics of a Mixed-Logic-Style Novel Adder Circuit at 90nm Gate Length
%J International Journal of Computer Applications
%@ 0975-8887
%V 119
%N 4
%P 27-33
%D 2015
%I Foundation of Computer Science (FCS), NY, USA
Abstract

This paper discusses a rail to rail swing, mixed logic style 1-bit 28-transistor (28T) full-adder, based on a novel architecture. The performance metrics: power, delay, and power delay product (PDP) of the proposed 1-bit adder is compared with other two high performance 1-bit adder architectures reported, till date. The proposed 1-bit adder has a 50% improvement in delay, and 49% improvement in power-delay-product, over the two reported architectures, verified at 90nm technology. The power performance of proposed 1-bit adder and that of the two reported architecture are comparable, within 8%. This analysis has been done at supply voltage VDD = 1. 2V, load capacitance CL=150fF, and at a maximum input signal frequency fMAX=200MHz. Also, the worst case performance metrics of the proposed 1-bit adder circuit is seen to be less sensitive to variations in VDD and CL, over a wide range from 0. 6V to 1. 8V, and from 0fF to 200fF, respectively.

References
  1. S. Goel, A. Kumar, and M. A. Bayoumi, "Design of robust, energy-efficient full adders for deep-submicrometer design using hybrid- CMOS logic style", IEEE Transaction on Very Large Scale Integration (VLSI) System, Vol. 14, no. 12, pp. 1309-1320, Dec. 2006.
  2. S. Goel, S. Gollamudi, A. Kumar, and M. A. Bayoumi, "On the design of low energy hybrid CMOS 1-bit full adder cells", in Proc. Midwest Symposium of Circuits and System, pp. 209-212, 2004.
  3. Myers RH, Montgomery DC, Response surface methodology: process and product optimization using designed experiments, 2nd ed. NY: John Wiley & Sons Inc. ; 2002.
  4. Box GEP, Draper NR, "Empirical model-building and response surfaces", International edition, New York: John Wiley and Sons Inc. ; 1987.
  5. Dipanjan Sengupta, and Resve Saleh, "Generalized Power Delay Metric–in Deep Submicron CMOS Design", IEEE Transaction on CAD of ICs and Systems, Vol. 6, No. 1, pp. 183-189, Jan. 2007.
  6. Mariano Aguirre-Hernandez and Monico Linares-Aranda, "CMOS Full–Adders for Energy-Efficient Arithmetic Applications", IEEE Transaction on Very Large Scale Integration (VLSI) System, Vol. 19, no. 4, pp. 718–721, April. 2011.
  7. Mariano Aguirre-Hernandez and Monico Linares-Aranda, "An alternative logic approach to implement high-speed low power full adder cells", in Proc. SBCCI, Florianopolis, Brazil, Sep. 2005, pp. 166-171.
  8. A. M. Shams and M. Bayoumi, "Performance evaluation of 1 bit CMOS adder cells", in Proc. IEEE ISCAS, Orlando, FL, May 1999, Vol. 1, pp. 27-30.
  9. A. M. Shams, T. K. Darwish, and M. Bayoumi, "Performance analysis of low-power 1-bit CMOS full adder cells", IEEE Transaction on Very Large Scale Integration (VLSI) System, Vol. 10, No. 1, pp. 20-29, Feb. 2002
Index Terms

Computer Science
Information Sciences

Keywords

Full-adder Mixed logic style 28T 1-bit adder Power delay product Worst-case delay Worst case power Carry dependant sum Input vector transition and Adder architecture.