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Area Efficient Design Analysis of Carry Look Ahead Adder
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 119 - Number 20 |
| Year of Publication: 2015 |
| Authors: Anku Bala, Rajesh Mehra |
10.5120/21180-4215
|
Anku Bala, Rajesh Mehra . Area Efficient Design Analysis of Carry Look Ahead Adder. International Journal of Computer Applications. 119, 20 ( June 2015), 1-4. DOI=10.5120/21180-4215
Abstract
This paper provides a low power solution for Very Large Scale Integration. Power consumption of a circuit and its area occupied are major constraints for a VLSI designer. So in this paper we focused mainly on these two parameters by using different design methodologies such as Fully Automatic, Semi-custom and Fully Custom. Addition is basic operation in any system, but it requires more time as the number of bits are increased. So we use carry look ahead adder to reduce the processing time in circuits like processors or any other circuit. Design of CLA adder using semi-custom and fully custom approach can reduce the area and power consumption to a great extent.
References
- C. Suba, S. Karthick, M. Prakash, "Analysis of Different Bit Carry Lookahead Adder with Reconfigurability in Low Power VLSI Using Verilog Code", International Journal of Innovative Research in Computer and Communication Engineering, ISSN (Print): 2320-9798, Vol. 2, Issue 11, November 2014, pp 6365-6371.
- Meena Aggarwal, Aastha Agarwal, Mr. Rajesh Mehra, "4-Input Decimal Adder Using 90 nm CMOS Technology", IOSR Journal of Engineering (IOSRJEN) e-ISSN: 2250-3021, p-ISSN: 2278-8719 Vol. 3, Issue 5(May. 2013), ||V4 || PP 48- 51.
- Laxmi Kumre, Ajay Somkuwar and Ganga Agnihotri, "Power Efficient Carry Propagate Adder", International Journal of VLSI design & Communication Systems (VLSICS) Vol. 4, No. 3, June 2013, pp 125-134.
- Rajender Kumar, Sandeep Dahiya, " Performance Analysis of Different Bit Carry Look Ahead Adder Using VHDL Environment", International Journal of Engineering Science and Innovative Technology (IJESIT) Volume 2, Issue 4, July 2013, pp 80-88
- Shilpa Thakur and Rajesh Mehra, "MOS Design And Single Supply Level Shifter Using 90nm Technology", Conference on Advances in Communication and Control Systems 2013 (CAC2S 2013), pp 150-153
- Dinesh Sharma and Rajesh Mehra, "Low Power, Delay Optimized Buffer Design using 70nm CMOS Technology", International Journal of Computer Applications (0975 – 8887) Volume 22– No. 3, May 2011, pp 13-18
- Itamar Levi, Ori Bass, Asaf Kaizerman, Alexander Belenky and Alexander Fish, "High Speed Dual Mode Logic Carry Look Ahead Adder", IEEE International Symposium on Circuits and Systems (ISCAS), 2012 , pp 3037 – 3040
- Jagannath Samanta, Mousam Halder, Bishnu Prasad De, "Performance Analysis of High Speed Low Power Carry Look-Ahead Adder Using Different Logic Styles", International Journal of Soft Computing and Engineering (IJSCE) ISSN: 2231-2307, Volume-2, Issue-6, Jan- 2013, pp 330-336
- Anjali Sharma Rajesh Mehra, "Area and Power Efficient CMOS Adder Design by Hybridizing PTL and GDI Technique", International Journal of Computer Applications (0975 – 8887) Volume 66– No. 4, March 2013, pp 15-22.
- R. UMA,Vidya Vijayan, M. Mohanapriya, Sharon Paul, "Area, Delay and Power Comparison of Adder Topologies", International Journal of VLSI design & Communication Systems (VLSICS) Vol. 3, No. 1, February 2012, pp 153-168.
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